Jiuren Zhou

Orcid: 0000-0002-0915-5354

According to our database1, Jiuren Zhou authored at least 20 papers between 2021 and 2026.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2026
DSPE: An Energy-Efficient Edge Processor for DeepSeek Inference with MerkleTree-based Incremental Pruning, Multi-Stage Boothing Lookup and Dynamic Adaptive Posit Processing.
CoRR, May, 2026

Collaborative Design of FeRAM via a Joint Ferroelectric Device and Circuit Analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., March, 2026

SPICA: Energy-Efficient SRAM-Based Multi-Precision Multi-Mode Compute-in-Memory Accelerator for AI Inference.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2026

FeRAM-Based Reconfigurable Strong PUF with Ultra-Low Power and Enhanced Attack Resilience.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2026

GATPE: A High-Performance Edge-Device GAT Processor with Multi-Layer Data-Variation Mechanism.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2026

GTPE: A 28nm 33.12 TFLOPS/W GNN Training Processor with Unstructured Multi Threshold Pruning, Hybrid Multi-mode Approximate Computing and QUIRE Number System Support.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2026

MPE: A Power-Efficient Edge-Device Mamba Processor with Multi-Dimensional Calculation-Compression Scheme.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2026

2025
Ferroelectric materials, devices, and chips technologies for advanced computing and memory applications: development and challenges.
Sci. China Inf. Sci., 2025

A parallel computing-in-memory accelerator utilizing FeRAM array with retention loss correction.
Sci. China Inf. Sci., 2025

GPE: A High-Performance Edge GNN Inference Processor with Multi-Parallelism Format-Variation Mechanism.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

STPE: An Energy-Efficient Edge-Device Transformer Inference Processor with Multi-Mode Data-Compression Scheme.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

UPE: A Device-Edge DNN Inference Artificial Intelligence Processor with Supporting Reconfigurable Training.
Proceedings of the 7th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2025

2024
Double-gated ferroelectric-gate field-effect-transistor for multi-bit content-addressable memories.
Microelectron. J., January, 2024

Enhanced fatigue resistance of ferroelectric Al0.65Sc0.35N deposited by physical vapor deposition.
Sci. China Inf. Sci., 2024

Accurate Charge-Domain Bootstrapped Computing-in-Memory SRAM Design with Wide Programmable Output Voltage Range.
Proceedings of the 37th IEEE International System-on-Chip Conference, 2024

GRS: A General RISC-V SIMD Vector Acceleration Processor for Artificial Intelligence Applications.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2024

SSPE: A Device-edge SNN Inference Artificial Intelligence Processor in Supporting Smart Computing.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2024

2022
Experimental Demonstration of An Inversion-Type Ferroelectric Capacitive Memory and its 1 kbit Crossbar Array Featuring High CHCS/CLCS, Fast Speed, and Long Retention.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

First Demonstration of Fully CMOS-compatible Non-volatile Programmable Photonic Switch Enabled by Ferroelectric-SOI Waveguide for Next Generation Photonic Integrated Circuit.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

2021
High mobility germanium-on-insulator p-channel FinFETs.
Sci. China Inf. Sci., 2021


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