Hari Vijay Venkatanarayanan

According to our database, Hari Vijay Venkatanarayanan authored at least 4 papers between 2006 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2025

TOGGLE6.0: A 4.8Gbps Next Generation Area and Power Efficient Transceiver for Flash Memory Interface.

Hari Vijay Venkatanarayanan, Rustum Prasad Sahu, Maheswara Alamuru, Ergam Reddy Battini, Syed Mohammed Haroon, Saurav Suman, Deepika Mallela, Sanjeeb Kumar Ghosh, Billy Koo

Proceedings of the 38th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems, 2025

2008

A Jitter Reduction Circuit Using Autocorrelation for Phase-Locked Loops and Serializer-Deserializer (SERDES) Circuits.

Hari Vijay Venkatanarayanan, Michael L. Bushnell

Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

2007

A Neural Net Branch Predictor to Reduce Power.

Rajamani Sethuram, Omar I. Khan, Hari Vijay Venkatanarayanan, Michael L. Bushnell

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

2006

An Area Efficient Mixed-Signal Test Architecture for Systems-on-a-Chip.

Hari Vijay Venkatanarayanan, Michael L. Bushnell

Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006