Rajamani Sethuram

According to our database, Rajamani Sethuram authored at least 8 papers between 2006 and 2011.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2011

Leakage power profiling and leakage power reduction using DFT hardware.

Rajamani Sethuram, Karim Arabi, Mohamed H. Abu-Rahma

Proceedings of the 29th IEEE VLSI Test Symposium, 2011

Trace Buffer-Based Silicon Debug with Lossless Compression.

Sandesh Prabhakar, Rajamani Sethuram, Michael S. Hsiao

Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011

2010

Scan Shift Power Reduction by Gating Internal Nodes.

Dheepakkumaran Jayaraman, Rajamani Sethuram, Spyros Tragoudas

J. Low Power Electron., 2010

Gating internal nodes to reduce power during scan shift.

Dheepakkumaran Jayaraman, Rajamani Sethuram, Spyros Tragoudas

Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

2008

Fault Nodes in Implication Graph for Equivalence/Dominance Collapsing, and Identifying Untestable and Independent Faults.

Rajamani Sethuram, Michael L. Bushnell, Vishwani D. Agrawal

Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

2007

Zero Cost Test Point Insertion Technique for Structured ASICs.

Rajamani Sethuram, Seongmoon Wang, Srimat T. Chakradhar, Michael L. Bushnell

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

A Neural Net Branch Predictor to Reduce Power.

Rajamani Sethuram, Omar I. Khan, Hari Vijay Venkatanarayanan, Michael L. Bushnell

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

2006

Zero Cost Test Point Insertion Technique to Reduce Test Set Size and Test Generation Time for Structured ASICs.

Rajamani Sethuram, Seongmoon Wang, Srimat T. Chakradhar, Michael L. Bushnell

Proceedings of the 15th Asian Test Symposium, 2006