Harish Kriplani

According to our database, Harish Kriplani authored at least 6 papers between 1990 and 2002.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2002

Timing model extraction of hierarchical blocks by graph reduction.

Cho W. Moon, Harish Kriplani, Krishna P. Belkhale

Proceedings of the 39th Design Automation Conference, 2002

1995

Pattern independent maximum current estimation in power and ground buses of CMOS VLSI circuits: Algorithms, signal correlations, and their resolution.

Harish Kriplani, Farid N. Najm, Ibrahim N. Hajj

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

1994

Improved Delay and Current Models for Estimating Maximum Currents in CMOS VLSI Circuits.

Harish Kriplani, Farid N. Najm, Ibrahim N. Hajj

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

1993

Resolving Signal Correlations for Estimating Maximum Currents in CMOS Combinational Circuits.

Harish Kriplani, Farid N. Najm, Ping Yang, Ibrahim N. Hajj

Proceedings of the 30th Design Automation Conference. Dallas, 1993

1992

Maximum Current Estimation in CMOS Circuits.

Harish Kriplani, Farid N. Najm, Ibrahim N. Hajj

Proceedings of the 29th Design Automation Conference, 1992

1990

Resource constrained design of artificial neural networks.

Benjamin W. Wah, Harish Kriplani

Proceedings of the IJCNN 1990, 1990