Harsh Shrivastav

Orcid: 0000-0001-5355-5825

According to our database1, Harsh Shrivastav authored at least 3 papers between 2021 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
Silicon-correlated Simulation Methodology of EM Side-channel Leakage Analysis.
ACM J. Emerg. Technol. Comput. Syst., January, 2023

2022
Layout-level Vulnerability Ranking from Electromagnetic Fault Injection.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2022

2021
Multiphysics Simulation of EM Side-Channels from Silicon Backside with ML-based Auto-POI Identification.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2021


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