Makoto Nagata
Orcid: 0000-0002-0625-9107
According to our database1,
Makoto Nagata
authored at least 179 papers
between 1998 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
-
on orcid.org
On csauthors.net:
Bibliography
2024
Electromagnetic Interference With the Mobile Communication Devices in Unmanned Aerial Vehicles and Its Countermeasures.
IEEE Access, 2024
On-Chip Evaluation of Voltage Drops and Fault Occurrence Induced by Si Backside EM Injection.
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2024
2023
Experimental Exploration of the Backside ESD Impacts on an IC Chip in Flip Chip Packaging.
IEICE Trans. Electron., October, 2023
An Analog Side-Channel Attack on a High-Speed Asynchronous SAR ADC Using Dual Neural Network Technique.
IEICE Trans. Electron., October, 2023
IEICE Trans. Electron., July, 2023
ACM J. Emerg. Technol. Comput. Syst., January, 2023
IEEE J. Solid State Circuits, 2023
Findings of the 2023 Conference on Machine Translation (WMT23): LLMs Are Here but Not Quite There Yet.
Proceedings of the Eighth Conference on Machine Translation, 2023
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
Proceedings of the IEEE International Reliability Physics Symposium, 2023
On the Unpredictability of SPICE Simulations for Side-Channel Leakage Verification of Masked Cryptographic Circuits.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
2022
IEEE Trans. Very Large Scale Integr. Syst., 2022
An 11-bit 0.008mm<sup>2</sup> charge-redistribution digital-to-analog converter operating at cryogenic temperature for large-scale qubit arrays.
IEICE Electron. Express, 2022
IEEE Des. Test, 2022
Proceedings of the IEEE International Reliability Physics Symposium, 2022
Proceedings of the IEEE International Reliability Physics Symposium, 2022
2021
Diffusional Side-Channel Leakage From Unrolled Lightweight Block Ciphers: A Case Study of Power Analysis on PRINCE.
IEEE Trans. Inf. Forensics Secur., 2021
Low-cost distance-spoofing attack on FMCW radar and its feasibility study on countermeasure.
J. Cryptogr. Eng., 2021
IEICE Electron. Express, 2021
Proceedings of the ACM/IEEE International Workshop on System Level Interconnect Prediction, 2021
Multiphysics Simulation of EM Side-Channels from Silicon Backside with ML-based Auto-POI Identification.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2021
Proceedings of the 26th IEEE European Test Symposium, 2021
2020
A Random Interrupt Dithering SAR Technique for Secure ADC Against Reference-Charge Side-Channel Attack.
IEEE Trans. Circuits Syst. II Express Briefs, 2020
IEEE Trans. Computers, 2020
Si-Backside Protection Circuits Against Physical Security Attacks on Flip-Chip Devices.
IEEE J. Solid State Circuits, 2020
A 0.6-V Adaptive Voltage Swing Serial Link Transmitter Using Near Threshold Body Bias Control and Jitter Estimation.
IEICE Trans. Electron., 2020
Fast and Comprehensive Simulation Methodology for Layout-Based Power-Noise Side-Channel Leakage Analysis.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2020
2019
IEEE Trans. Very Large Scale Integr. Syst., 2019
Side-channel leakage from sensor-based countermeasures against fault injection attack.
Microelectron. J., 2019
A 0.72pJ/bit 400μm<sup>2</sup> Physical Random Number Generator Utilizing SAR Technique for Secure Implementation on Sensor Nodes.
IEICE Trans. Electron., 2019
Deployment of EMC-Compliant IC Chip Techniques in Design for Hardware Security - Invited Paper.
Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2019
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019
Proceedings of the 3rd ACM Workshop on Attacks and Solutions in Hardware Security Workshop, 2019
On-Chip Protection of Cryptographic ICs Against Physical Side Channel Attacks: Invited Paper.
Proceedings of the 13th IEEE International Conference on ASIC, 2019
Over-the-top Si Interposer Embedding Backside Buried Metal PDN to Reduce Power Supply Impedance of Large Scale Digital ICs.
Proceedings of the 2019 International 3D Systems Integration Conference (3DIC), 2019
2018
A Demonstration of a HT-Detection Method Based on Impedance Measurements of the Wiring Around ICs.
IEEE Trans. Circuits Syst. II Express Briefs, 2018
Chip-Package-Board Interactive PUF Utilizing Coupled Chaos Oscillators With Inductor.
IEEE J. Solid State Circuits, 2018
A 286 F<sup>2</sup>/Cell Distributed Bulk-Current Sensor and Secure Flush Code Eraser Against Laser Fault Injection Attack on Cryptographic Processor.
IEEE J. Solid State Circuits, 2018
IEICE Electron. Express, 2018
Session 31 overview: Computation in memory for machine learning: Technology directions and memory subcommittees.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
Session 30 overview: Emerging memories: Memory and technology directions subcommittees.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
Session 17 overview: Technologies for health and society: Technology directions subcommittee.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
A 286F<sup>2</sup>/cell distributed bulk-current sensor and secure flush code eraser against laser fault injection attack.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
Session 21 overview: Extending silicon and its applications: Technology directions subcommittee.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018
2017
Design Methodology and Validity Verification for a Reactive Countermeasure Against EM Attacks.
J. Cryptol., 2017
A 500 MHz-BW -52.5 dB-THD Voltage-to-Time Converter Utilizing Two-Step Transition Inverter Delay Lines in 28 nm CMOS.
IEICE Trans. Electron., 2017
IEICE Electron. Express, 2017
15.8 A permanent digital archive system based on 4F<sup>2</sup> x-point multi-layer metal nano-dot structure.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
Exploiting Bitflip Detector for Non-invasive Probing and its Application to Ineffective Fault Analysis.
Proceedings of the 2017 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2017
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
2016
A Novel Methodology for Testing Hardware Security and Trust Exploiting On-Chip Power Noise Measurements (Extended Version).
IACR Cryptol. ePrint Arch., 2016
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
Proceedings of the 2016 IEEE Asian Hardware-Oriented Security and Trust, 2016
Ring Oscillator under Laser: Potential of PLL-based Countermeasure against Laser Fault Injection.
Proceedings of the 2016 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2016
A 500MHz-BW -52.5dB-THD Voltage-to-Time Converter utilizing a two-step transition inverter.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016
Proceedings of the 53rd Annual Design Automation Conference, 2016
2015
An Extended Direct Power Injection Method for In-Place Susceptibility Characterization of VLSI Circuits Against Electromagnetic Interference.
IEEE Trans. Very Large Scale Integr. Syst., 2015
A Silicon-Level Countermeasure Against Fault Sensitivity Analysis and Its Evaluation.
IEEE Trans. Very Large Scale Integr. Syst., 2015
A 1 mm Pitch 80 × 80 Channel 322 Hz Frame-Rate Multitouch Distribution Sensor With Two-Step Dual-Mode Capacitance Scan.
IEEE J. Solid State Circuits, 2015
IEEE Des. Test, 2015
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
Proceedings of the 2015 IEEE International Conference on Acoustics, 2015
Analysis of on-chip digital noise coupling path for wireless communication IC test chip.
Proceedings of the 10th International Workshop on the Electromagnetic Compatibility of Integrated Circuits, 2015
Proceedings of the 52nd Annual Design Automation Conference, 2015
A novel methodology for testing hardware security and trust exploiting On-Chip Power noise Measurement.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
A DPA/DEMA/LEMA-resistant AES cryptographic processor with supply-current equalizer and micro EM probe sensor.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
Proceedings of the 2015 International 3D Systems Integration Conference, 2015
2014
Introduction to the Special Issue on the 2014 IEEE International Solid-State Circuits Conference (ISSCC).
IEEE J. Solid State Circuits, 2014
AC Power Supply Noise Simulation of CMOS Microprocessor with LSI Chip-Package-Board Integrated Model.
IEICE Trans. Electron., 2014
Diagnosis of Signaling and Power Noise Using In-Place Waveform Capturing for 3D Chip Stacking.
IEICE Trans. Electron., 2014
A 40-nm Resilient Cache Memory for Dynamic Variation Tolerance Delivering ×91 Failure Rate Improvement under 35% Supply Voltage Fluctuation.
IEICE Trans. Electron., 2014
Power Noise Measurements of Cryptographic VLSI Circuits Regarding Side-Channel Information Leakage.
IEICE Trans. Electron., 2014
Chip Level Simulation of Substrate Noise Coupling and Interference in RF ICs with CMOS Digital Noise Emulator.
IEICE Trans. Electron., 2014
IEICE Electron. Express, 2014
EM Attack Is Non-Invasive? - Design Methodology and Validity Verification of EM Attack Sensor.
IACR Cryptol. ePrint Arch., 2014
A local EM-analysis attack resistant cryptographic engine with fully-digital oscillator-based tamper-access sensor.
Proceedings of the Symposium on VLSI Circuits, 2014
A passive supply-resonance suppression filter utilizing inductance-enhanced coupled bonding-wire coils.
Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014
12.4 A 1mm-pitch 80×80-channel 322Hz-frame-rate touch sensor with two-step dual-mode capacitance scan.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
A 40-nm resilient cache memory for dynamic variation tolerance with bit-enhancing memory and on-chip diagnosis structures delivering ×91 failure rate improvement.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014
Proceedings of the 2014 IEEE International Symposium on Hardware-Oriented Security and Trust, 2014
Physical Security Evaluation at an Early Design-Phase: A Side-Channel Aware Simulation Methodology.
Proceedings of the International Workshop on Engineering Simulations for Cyber-Physical Systems, 2014
On-Chip Monitoring for In-Place Diagnosis of Undesired Power Domain Problems in IC Chips.
Proceedings of the 23rd IEEE Asian Test Symposium, 2014
An intermittent-driven supply-current equalizer for 11x and 4x power-overhead savings in CPA-resistant 128bit AES cryptographic processor.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014
2013
Measurements and Simulation of Sensitivity of Differential-Pair Transistors against Substrate Voltage Variation.
IEICE Trans. Electron., 2013
Design of Effective Supply Voltage Monitor for Measuring Power Rails of Integrated Circuits.
IEICE Trans. Electron., 2013
A Fast Power Current Simulation of Cryptographic VLSI Circuits for Side Channel Attack Evaluation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013
Equivalent Circuit Representation of Silicon Substrate Coupling of Passive and Active RF Components.
IEICE Trans. Electron., 2013
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013
Proceedings of the 2013 IEEE International Test Conference, 2013
A 100GB/s wide I/O with 4096b TSVs through an active silicon interposer with in-place waveform capturing.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
Proceedings of the 9th International Workshop on Electromagnetic Compatibility of Integrated Circuits, 2013
Measurement-based diagnosis of wireless communication performance in the presence of in-band interferers in RF ICs.
Proceedings of the 9th International Workshop on Electromagnetic Compatibility of Integrated Circuits, 2013
Proceedings of the 9th International Workshop on Electromagnetic Compatibility of Integrated Circuits, 2013
Proceedings of the 9th International Workshop on Electromagnetic Compatibility of Integrated Circuits, 2013
Measurements and simulation of substrate noise coupling in RF ICs with CMOS digital noise emulator.
Proceedings of the 9th International Workshop on Electromagnetic Compatibility of Integrated Circuits, 2013
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013
2012
IEEE J. Solid State Circuits, 2012
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012
IEICE Trans. Electron., 2012
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012
On-Chip In-Place Measurements of V<sub>th</sub> and Signal/Substrate Response of Differential Pair Transistors.
IEICE Trans. Electron., 2012
2011
An On-Chip Waveform Capturer and Application to Diagnosis of Power Delivery in SoC Integration.
IEEE J. Solid State Circuits, 2011
On-Chip Single Tone Pseudo-Noise Generator for Analog IP Noise Tolerance Measurement.
IEICE Trans. Electron., 2011
A Diagnosis Testbench of Analog IP Cores for Characterization of Substrate Coupling Strength.
IEICE Trans. Electron., 2011
A Continuous-Time Waveform Monitoring Technique for On-Chip Power Noise Measurements in VLSI Circuits.
IEICE Trans. Electron., 2011
IEICE Electron. Express, 2011
Proceedings of the 29th IEEE VLSI Test Symposium, 2011
Accurate analysis of substrate sensitivity of active transistors in an analog circuit.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011
A fast power current analysis methodology using capacitor charging model for side channel attack evaluation.
Proceedings of the HOST 2011, 2011
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011
2010
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010
IEICE Trans. Electron., 2010
IEICE Trans. Electron., 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
2009
Experimental Evaluation of Dynamic Power Supply Noise and Logical Failures in Microprocessor Operations.
IEICE Trans. Electron., 2009
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009
A full chip integrated power and substrate noise analysis framework for mixed-signal SoC design.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009
2008
Current-Mode Transceiver with Nonfeedback Clock Recovery Capability for Mobile Applications.
IEICE Trans. Electron., 2008
IEICE Trans. Electron., 2008
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008
2007
An On-Chip Multichannel Waveform Monitor for Diagnosis of Systems-on-a-Chip Integration.
IEEE Trans. Very Large Scale Integr. Syst., 2007
On-Chip Multi-Channel Monitoring for Analog Circuit Diagnosis in Systems-on-Chip Integration.
IEICE Trans. Electron., 2007
Asymmetric Slope Dual Mode Differential Logic Circuit for Compatibility of Low-Power and High-Speed Operations.
IEICE Trans. Electron., 2007
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007
Evaluation of Isolation Structures against High-Frequency Substrate Coupling in Analog/Mixed-Signal Integrated Circuits.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007
Substrate-Noise and Random-Variability Reduction with Self-Adjusted Forward Body Bias.
IEICE Trans. Electron., 2007
Experimental Verification of Power Supply Noise Modeling for EMI Analysis through On-Board and On-Chip Noise Measurements.
IEICE Trans. Electron., 2007
A Mixed Circuit and System Level Simulation Technique of Collision-Resistant RFID System.
IEICE Trans. Electron., 2007
On-Die Supply-Voltage Noise Sensor with Real-Time Sampling Mode for Low-Power Processor Applications.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
Fine-Grained In-Circuit Continuous-Time Probing Technique of Dynamic Supply Variations in SoCs.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
Proceedings of the 44th Design Automation Conference, 2007
Chip-Level Substrate Noise Analysis with Emphasis of Vertical Impurity Profile for Isolation.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007
2006
Proc. IEEE, 2006
An Integrated Timing and Dynamic Supply Noise Verification for Multi-10-Million Gate SoC Designs.
IEICE Trans. Electron., 2006
An On-Chip Multi-Channel Rail-to-Rail Signal Monitoring Technique for Sub-100-nm Digital Signal Integrity.
IEICE Trans. Electron., 2006
IEICE Trans. Electron., 2006
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006
Back-End Design of a Collision-Resistive RFID System through High-Level Modeling Approach.
IEICE Trans. Electron., 2006
IEICE Trans. Electron., 2006
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006
Equivalent circuit modeling of guard ring structures for evaluation of substrate crosstalk isolation.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006
2005
A built-in technique for probing power supply and ground noise distribution within large-scale digital integrated circuits.
IEEE J. Solid State Circuits, 2005
J. Robotics Mechatronics, 2005
Dynamic Power-Supply and Well Noise Measurements and Analysis for Low Power Body Biased Circuits.
IEICE Trans. Electron., 2005
Logic Synthesis Technique for High Speed Differential Dynamic Logic with Asymmetric Slope Transition.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005
High-Speed Digital Circuit Design Using Differential Logic with Asymmetric Signal Transition.
IEICE Trans. Electron., 2005
Proceedings of the 31st European Solid-State Circuits Conference, 2005
On-Chip Multi-Channel Waveform Monitoring for Diagnostics of Mixed-Signal VLSI Circuits.
Proceedings of the 2005 Design, 2005
An integrated timing and dynamic supply noise verification for nano-meter CMOS SoC designs.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005
Substrate-noise and random-fluctuations reduction with self-adjusted forward body bias.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005
2004
Full-chip vectorless dynamic power integrity analysis and verification against 100uV/100ps-resolution measurement.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004
2003
Proceedings of the IEEE Custom Integrated Circuits Conference, 2003
2002
Image Segmentation/Extraction Using Nonlinear Cellular Networks and Their VLSI Implementation Using Pulse-Modulation Techniques.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002
Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002
A cellular-automaton-type image extraction algorithm and its implementation using an FPGA.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002
2001
IEEE J. Solid State Circuits, 2001
A PWM analog memory programming circuit for floating-gate MOSFETs with 75-μs programming time and 11-bit updating resolution.
IEEE J. Solid State Circuits, 2001
An Efficient Clustering Algorithm Using Stochastic Association Model and Its Implementation Using Nanostructures.
Proceedings of the Advances in Neural Information Processing Systems 14 [Neural Information Processing Systems: Natural and Synthetic, 2001
Chip-Level Substrate Noise Analysis with Network Reduction by Fundamental Matrix Computation.
Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001
Proceedings of ASP-DAC 2001, 2001
2000
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000
Pulse modulation circuit architecture and its application to functional image sensors.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Quantitative characterization of substrate noise for physical design guides in digital circuits.
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000
Proceedings of ASP-DAC 2000, 2000
Substrate crosstalk analysis in mixed signal CMOS integrated circuits: embedded tutorial.
Proceedings of ASP-DAC 2000, 2000
Proceedings of ASP-DAC 2000, 2000
1999
A Feature Associative Processor for Image Recognition Based on A-D merged Architecture.
Proceedings of the VLSI: Systems on a Chip, 1999
Measurements and analyses of substrate noise waveform in mixed signal IC environment.
Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, 1999
1998
A PWM signal processing core circuit based on a switched current integration technique.
IEEE J. Solid State Circuits, 1998
Nonlinear Function Generators and Chaotic Signal Generators Based on Pulse-Phase Modulation.
Proceedings of the Fifth International Conference on Neural Information Processing, 1998
Oscillator Networks for Image Segmentation and Their Circuits Using Pulse Modulation Method.
Proceedings of the Fifth International Conference on Neural Information Processing, 1998