Heinrich Klar

According to our database, Heinrich Klar authored at least 21 papers between 1993 and 2016.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2016

Implementation and design investigation of 40 Gbps driver IC for silicon photonics ring-modulator in SiGe 130-nm.

Adel Fatemi, Heinrich Klar, Friedel Gerfers

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2005

A cascade 3-1-1 multibit ΣΔ A/D modulator with reduced sensitivity to non-idealities.

Yi Yin, Heinrich Klar, Peter Wennekers

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004

A novel broadband cascade sigma-delta analog-to-digital converter.

Yi Yin, Heinrich Klar, Peter Wennekers

Proceedings of the Second IASTED International Conference on Circuits, 2004

2003

Synaptic plasticity in spiking neural networks (SP²INN): a system approach.

Nasser Mehrtash, Dietmar Jung, Heik Heinrich Hellmich, Tim Schönauer, Vi Thanh Lu, Heinrich Klar

IEEE Trans. Neural Networks, 2003

Image preprocessing with dynamic synapses.

Nasser Mehrtash, Dietmar Jung, Heinrich Klar

Neural Comput. Appl., 2003

2002

NeuroPipe-Chip: A digital neuro-processor for spiking neural networks.

Tim Schönauer, Sahin Atasoy, Nasser Mehrtash, Heinrich Klar

IEEE Trans. Neural Networks, 2002

Simulation of spiking neural networks -- architectures and implementations.

Martin Schäfer, Tim Schönauer, Carsten Wolff, Georg Hartmann, Heinrich Klar, Ulrich Rückert

Neurocomputing, 2002

2000

Simulation of a Digital Neuro-Chip for Spiking Neural Networks.

Tim Schönauer, Sahin Atasoy, Nasser Mehrtash, Heinrich Klar

Proceedings of the IEEE-INNS-ENNS International Joint Conference on Neural Networks, 2000

1998

A 12-bit medium-time analog storage device in a CMOS standard process.

Martin Ehlert, Heinrich Klar

IEEE J. Solid State Circuits, 1998

1997

A New Bio-inspired Algorithm for Early Vision Edge Detection and Image Segmentation.

Chang-Han Yi, Robert Schlabbach, Holger Kroth, Heinrich Klar

Proceedings of the Biological and Artificial Computation: From Neuroscience to Technology, 1997

Dynamic Path Planning with Spiking Neural Networks.

Ulrich Roth, Marc Walker, Arne Hilmann, Heinrich Klar

Proceedings of the Biological and Artificial Computation: From Neuroscience to Technology, 1997

An Improved Multiplexed Resistive Network for Analog Image Preprocessing.

Chang-Han Yi, Robert Schlabbach, Holger Kroth, Heinrich Klar

Proceedings of the Artificial Neural Networks, 1997

On-Line Hebbian Learning for Spiking Neurons: Architecture of the Weight-Unit of NESPINN.

Ulrich Roth, Axel Jahnke, Heinrich Klar

Proceedings of the Artificial Neural Networks, 1997

Simulation of Spiking Neural Networks on Different Hardware Platforms.

Axel Jahnke, Tim Schönauer, Ulrich Roth, K. Mohraz, Heinrich Klar

Proceedings of the Artificial Neural Networks, 1997

1996

A CMOS gate array architecture for digital signal processing applications.

Jorg-Michael Green, Heinrich Klar

IEEE J. Solid State Circuits, 1996

1995

General algorithms for a simplified addition of 2's complement numbers.

O. Salomon, Jorg-Michael Green, Heinrich Klar

IEEE J. Solid State Circuits, July, 1995

Calculation of the soft error rate of submicron CMOS logic circuits.

T. Juhnke, Heinrich Klar

IEEE J. Solid State Circuits, July, 1995

Hardware Requirements for Spike-Processing Neural Networks.

Ulrich Roth, Axel Jahnke, Heinrich Klar

Proceedings of the From Natural to Artificial Neural Computation, 1995

A new algorithm for the design of stable higher order single loop sigma delta analog-to-digital converters.

S. R. Kadivar, Doris Schmitt-Landsiedel, Heinrich Klar

Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

1993

Design of a general-purpose neural signal processor.

Jörg Beichter, Nico Brüls, Elisabeth Sicheneder, Ulrich Ramacher, Heinrich Klar

Neurocomputing, 1993

Self-Timed Fully Pipelined Multipliers.

O. Salomon, Heinrich Klar

Proceedings of the Asynchronous Design Methodologies, Proceedings of the IFIP WG10.5 Working Conference on Asynchronous Design Methodologies, Manchester, UK, 31 March, 1993