Hendrik van der Ploeg

According to our database, Hendrik van der Ploeg authored at least 6 papers between 1999 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2025

A 6-GHz Continuous-Time Bandpass ΔΣ ADC With Background Filter Calibration and -100 dBc IM3 for a Mixer-Less DAB Band III Receiver.

Shagun Bajoria, Robert Rutten, Muhammed Bolatkale, Yihan Gao, Hans Brekelmans, Bernard Burdiek, Hendrik van der Ploeg, Lucien J. Breems

IEEE J. Solid State Circuits, July, 2025

2009

A 1.2-V 250-mW 14-b 100-MS/s Digitally Calibrated Pipeline ADC in 90-nm CMOS.

Hans Van de Vel, Berry A. J. Buter, Hendrik van der Ploeg, Maarten Vertregt, Govert J. G. M. Geelen, Edward J. F. Paulus

IEEE J. Solid State Circuits, 2009

2006

A 15-bit 30-MS/s 145-mW three-step ADC for imaging applications.

Hendrik van der Ploeg, Maarten Vertregt, Marco Lammers

IEEE J. Solid State Circuits, 2006

2003

A 1.8V 100mW 12-bits 80Msample/s two-step ADC in 0.18-μm CMOS.

Amir Zjajo, Hendrik van der Ploeg, Maarten Vertregt

Proceedings of the ESSCIRC 2003, 2003

2001

A 2.5-V 12-b 54-Msample/s 0.25-μm CMOS ADC in 1-mm² with mixed-signal chopping and calibration.

Hendrik van der Ploeg, Gian Hoogzaad, Henk A. H. Termeer, Maarten Vertregt, Raf L. J. Roovers

IEEE J. Solid State Circuits, 2001

1999

A 3.3-V, 10-b, 25-MSample/s two-step ADC in 0.35-μm CMOS.

Hendrik van der Ploeg, Robert Remmers

IEEE J. Solid State Circuits, 1999