Amir Zjajo

According to our database1, Amir Zjajo authored at least 65 papers between 2005 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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On csauthors.net:

Bibliography

2019
Towards Robust Inference of Biomedical Signals in Energy-Efficient Neuromorphic Networks.
Proceedings of the IEEE 1st Global Conference on Life Sciences and Technologies, 2019

Heterogeneous Activation Function Extraction for Training and Optimization of SNN Systems.
Proceedings of the IEEE International Conference on Artificial Intelligence Circuits and Systems, 2019

Neurosynaptic Computational Elements for Adaptive Transient Synchrony: Biophysical Accuracy versus Hardware Complexity.
Proceedings of the 11th IEEE International Workshop on Computational Intelligence and Applications, 2019

Towards Computationally-Efficient Cognitive Sensor Systems for Autonomous Vehicles.
Proceedings of the 18th IEEE International Conference on Cognitive Informatics & Cognitive Computing, 2019

2018
A Real-Time Reconfigurable Multichip Architecture for Large-Scale Biophysically Accurate Neuron Simulation.
IEEE Trans. Biomed. Circuits Syst., 2018

Uncertainty in Noise-Driven Steady-State Neuromorphic Network for ECG Data Classification.
Proceedings of the 31st IEEE International Symposium on Computer-Based Medical Systems, 2018

Energy-efficient multipath ring network for heterogeneous clustered neuronal arrays.
Proceedings of the 2018 IEEE EMBS International Conference on Biomedical & Health Informatics, 2018

2017
Fighting Dark Silicon: Toward Realizing Efficient Thermal-Aware 3-D Stacked Multiprocessors.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Immediate Neighborhood Temperature Adaptive Routing for Dynamically Throttled 3-D Networks-on-Chip.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

Digital spiking neuron cells for real-time reconfigurable learning networks.
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

Neuromorphic self-organizing map design for classification of bioelectric-timescale signals.
Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017

Energy-efficient neuromorphic receptors for wide-range temporal patterns of post-synaptic responses.
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2017

Neuromorphic spike data classifier for reconfigurable brain-machine interface.
Proceedings of the 8th International IEEE/EMBS Conference on Neural Engineering, 2017

2016
Power-Efficiency of Signal Processing Circuits in Implantable Multichannel Brain-Machine Interface.
J. Low Power Electron., 2016

A 2.7μW 10b 640kS/s time-based A/D converter for implantable neural recording interface.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Multi-chip dataflow architecture for massive scale biophysically accurate neuron simulation.
Proceedings of the 38th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2016

A real-time hybrid neuron network for highly parallel cognitive systems.
Proceedings of the 38th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2016

A 2.1 μW/channel current-mode integrated neural recording interface.
Proceedings of the 2016 IEEE-EMBS International Conference on Biomedical and Health Informatics, 2016

A 41 μW real-time adaptive neural spike classifier.
Proceedings of the 2016 IEEE-EMBS International Conference on Biomedical and Health Informatics, 2016

2015
Multi-Domain SystemC model of 128-channel time-multiplexed neural interface front-end.
Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015

Ctherm: An Integrated Framework for Thermal-Functional Co-simulation of Systems-on-Chip.
Proceedings of the 23rd Euromicro International Conference on Parallel, 2015

Sequential power per area optimization of multichannel neural recording interface based on dual quadratic programming.
Proceedings of the 7th International IEEE/EMBS Conference on Neural Engineering, 2015

Stochastic noise analysis of neural interface front end.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Physical characterization of steady-state temperature profiles in three-dimensional integrated circuits.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Iterative learning cascaded multiclass kernel based support vector machine for neural spike data classification.
Proceedings of the IEEE Conference on Computational Intelligence in Bioinformatics and Computational Biology, 2015

Low Power Programmable Gain Analog to Digital Converter for Integrated Neural Implant Front End.
Proceedings of the Biomedical Engineering Systems and Technologies, 2015

Noise Analysis of Programmable Gain Analog to Digital Converter for Integrated Neural Implant Front End.
Proceedings of the BIODEVICES 2015, 2015

2014
Dynamic Thermal Estimation Methodology for High-Performance 3-D MPSoC.
IEEE Trans. Very Large Scale Integr. Syst., 2014

System Level Methodology for Interconnect Aware and Temperature Constrained Power Management of 3-D MP-SOCs.
IEEE Trans. Very Large Scale Integr. Syst., 2014

Considering Crosstalk Effects in Statistical Timing Analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Statistical Transistor-Level Timing Analysis Using a Direct Random Differential Equation Solver.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Statistical power optimization of deep-submicron digital CMOS circuits based on structured perceptron.
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

A 0.1pJ Freeze Vernier time-to-digital converter in 65nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

ESL design of customizable real-time neuron networks.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2014

2013
Adaptive Thermal Monitoring of Deep-Submicron CMOS VLSI Circuits.
J. Low Power Electron., 2013

A CMOS 0.23pj Freeze Vernier Time-To-Digital Converter.
Proceedings of the 2013 NORCHIP, Vilnius, Lithuania, November 11-12, 2013, 2013

Balanced stochastic truncation of coupled 3D interconnect.
Proceedings of 2013 International Conference on IC Design & Technology, 2013

2012
Low-Power Die-Level Process Variation and Temperature Monitors for Yield Analysis and Optimization in Deep-Submicron CMOS.
IEEE Trans. Instrum. Meas., 2012

Digital Adaptive Calibration of Multi-Step Analog to Digital Converters.
J. Low Power Electron., 2012

Stimulus generation for RF MEMS switches test application.
Int. J. Simul. Process. Model., 2012

ADC Multi-Site Test Based on a Pre-test with Digital Input Stimulus.
J. Electron. Test., 2012

Direct Statistical Simulation of Timing Properties in Sequential Circuits.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2012

Thermal analysis of 3D integrated circuits based on discontinuous Galerkin finite element method.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

A 11 µW 0°C-160°C temperature sensor in 90 nm CMOS for adaptive thermal monitoring of VLSI circuits.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Transistor-level gate model based statistical timing analysis considering correlations.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Crosstalk-aware statistical interconnect delay calculation.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011
Stochastic Analysis of Deep-Submicrometer CMOS Process for Reliable Circuits Designs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

A 1.2v 55mW 12bits self-calibrated dual-residue analog to digital converter in 90 nm CMOs.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

Pseudo circuit model for representing uncertainty in waveforms.
Proceedings of the Design, Automation and Test in Europe, 2011

2010
Statistical Moment Estimation of Delay and Power in Circuit Simulation.
J. Low Power Electron., 2010

Transistor-Level Gate Modeling for Nano CMOS Circuit Verification Considering Statistical Process Variations.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2010

A low-power digitally-programmable variable gain amplifier in 65 nm CMOS.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

Digital cartesian feedback linearization of switched mode power amplifiers.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

RDE-based transistor-level gate simulation for statistical static timing analysis.
Proceedings of the 47th Design Automation Conference, 2010

Noise analysis of non-linear dynamic integrated circuits.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009
Analog Automatic Test Pattern Generation for Quasi-Static Structural Test.
IEEE Trans. Very Large Scale Integr. Syst., 2009

Algorithms for ADC Multi-site Test with Digital Input Stimulus.
Proceedings of the 14th IEEE European Test Symposium, 2009

2008
Diagnostic analysis of bandwidth mismatch in time-interleaved systems.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

Calibration and Debugging of Multi-step Analog to Digital Converters.
Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008

Efficient Estimation of Die-Level Process Parameter Variations via the EM-Algorithm.
Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008

Diagnostic Analysis of Static Errors in Multi-Step Analog to Digital Converters.
Proceedings of the Design, Automation and Test in Europe, 2008

2007
Interactive presentation: BIST method for die-level process parameter variation monitoring in analog/mixed-signal integrated circuits.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006
Structural Fault Modeling and Fault Detection Through Neyman-Pearson Decision Criteria for Analog Integrated Circuits.
J. Electron. Test., 2006

2005
Power-scan chain: design for analog testability.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Evaluation of signature-based testing of RF/analog circuits.
Proceedings of the 10th European Test Symposium, 2005


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