Hidemi Ishiuchi

According to our database, Hidemi Ishiuchi authored at least 3 papers between 1990 and 2004.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2004

Low power logic circuit and SRAM cell applications with silicon on depletion layer CMOS (SODEL CMOS) technology.

Satoshi Inaba, Hajime Nagano, Kiyotaka Miyano, Ichiro Mizushima, Yasunori Okayama, Takahiro Nakauchi, Kazunari Ishimaru, Hidemi Ishiuchi

Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

1999

CMOS/BiCMOS Technology.

Yasuhiro Katsumata, Tatsuya Ohguro, Kazumi Inoh, Eiji Morifuji, Takashi Yoshitomi, Hideki Kimijima, Hideaki Nii, Toyota Morimoto, Hisayo S. Momose, Kuniyoshi Yoshikawa, Hidemi Ishiuchi, Hiroshi Iwai

Proceedings of the VLSI Handbook., 1999

1990

A latch-up-like new failure mechanism for high-density CMOS dynamic RAMs.

Tohru Furuyama, Hidemi Ishiuchi, Hiroyasu Tanaka, Yoshihisa Watanabe, Yusuke Kohyama, Tohru Kimura, Kazuyoshi Muraoka, Souichi Sugiura, Kenji Natori

IEEE J. Solid State Circuits, February, 1990