Yoshihisa Watanabe

According to our database1, Yoshihisa Watanabe authored at least 8 papers between 2006 and 2016.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2016
A Low Power 64 Gb MLC NAND-Flash Memory in 15 nm CMOS Technology.
IEEE J. Solid State Circuits, 2016

2015

2012
A 151-mm<sup>2</sup> 64-Gb 2 Bit/Cell NAND Flash Memory in 24-nm CMOS Technology.
IEEE J. Solid State Circuits, 2012


2011

2008
Blind Channel Shortening for Block Transmission of Correlated Signals.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

2007
A 56-nm CMOS 99-mm<sup>2</sup> 8-Gb Multi-Level NAND Flash Memory With 10-MB/s Program Throughput.
IEEE J. Solid State Circuits, 2007

2006


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