Tohru Kimura
According to our database1,
Tohru Kimura
authored at least 6 papers
between 1994 and 2008.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2008
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
1996
A 60-ns 1-Mb nonvolatile ferroelectric memory with a nondriven cell plate line write/read scheme.
IEEE J. Solid State Circuits, 1996
1995
Design of 1.28-GB/s high bandwidth 2-Mb SRAM for integrated memory array processor applications.
IEEE J. Solid State Circuits, June, 1995
1994
A 3.84 GIPS integrated memory array processor with 64 processing elements and a 2-Mb SRAM.
IEEE J. Solid State Circuits, November, 1994
IEEE J. Solid State Circuits, November, 1994