Hideo Nakane

According to our database, Hideo Nakane authored at least 4 papers between 2000 and 2014.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2014

A Fully Integrated SAR ADC Using Digital Correction Technique for Triple-Mode Mobile Transceiver.

Hideo Nakane, Ryuichi Ujiie, Takashi Oshima, Takaya Yamamoto, Keisuke Kimura, Yuichi Okuda, Kosuke Tsuiji, Tatsuji Matsuura

IEEE J. Solid State Circuits, 2014

2007

A Second-Order Multibit Complex Bandpass DeltaSigmaAD Modulator with I, Q Dynamic Matching and DWA Algorithm.

Hao San, Yoshitaka Jingu, Hiroki Wada, Hiroyuki Hagiwara, Akira Hayakawa, Haruo Kobayashi, Tatsuji Matsuura, Kouichi Yahagi, Junya Kudoh, Hideo Nakane, Masao Hotta, Toshiro Tsukada, Koichiro Mashiko, Atsushi Wada

IEICE Trans. Electron., 2007

2006

Complex Bandpass DeltaSigmaAD Modulator Architecture without I, Q-Path Crossing Layout.

Hao San, Akira Hayakawa, Yoshitaka Jingu, Hiroki Wada, Hiroyuki Hagiwara, Kazuyuki Kobayashi, Haruo Kobayashi, Tatsuji Matsuura, Kouichi Yahagi, Junya Kudoh, Hideo Nakane, Masao Hotta, Toshiro Tsukada, Koichiro Mashiko, Atsushi Wada

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

2000

A low-voltage fully-differential current-mode analog CMOS integrator using floating-gate MOSFETs.

Takahiro Inoue, Hideo Nakane, Yuuji Fukuju

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000