Hao San

Orcid: 0000-0001-7024-3444

According to our database¹, Hao San authored at least 46 papers between 1999 and 2023.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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In proceedings

Article

PhD thesis

Dataset

Other

Bibliography

2023

Thermal Noise Analysis of Ring Amplifier in Cyclic Analog-to-Digital Converter.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., May, 2023

2022

A Study on the Efficient Design of Adders Using Adiabatic Quantum-Flux-Parametron Circuits.

[BibT_eX]

[DOI]

Proceedings of the 11th IEEE Global Conference on Consumer Electronics, 2022

2021

A Low-voltage Non-binary Cyclic ADC using Fully Differential Ring Amplifier.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Intelligent Signal Processing and Communication Systems, 2021

A 0.7V 14bit Hybrid ADC in 65nm SOTB CMOS.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Intelligent Signal Processing and Communication Systems, 2021

A 0.8V 14bit 294kSPS non-binary cyclic ADC in 65nm SOTB CMOS technology.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Intelligent Signal Processing and Communication Systems, 2021

Linearity Compensation for Conversion Error in Non-binary and Binary Hybrid ADC.

[BibT_eX]

[DOI]

Yuanchi Chen

Hao San

Proceedings of the International Symposium on Intelligent Signal Processing and Communication Systems, 2021

2020

Foreword.

[BibT_eX]

[DOI]

Hao San

IEICE Trans. Electron., 2020

2019

A 6th-Order Quadrature Bandpass Delta Sigma AD Modulator Using Dynamic Amplifier and Noise Coupling SAR Quantizer.

[BibT_eX]

[DOI]

Chunhui Pan

Hao San

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019

Experimental implementation of delta sigma AD modulator using dynamic analog components with simplified operation phase.

[BibT_eX]

[DOI]

Chunhui Pan

Hao San

IEICE Electron. Express, 2019

A 0.8V 14bit 62.5kSPS non-binary cyclic ADC using SOTB CMOS technology.

[BibT_eX]

[DOI]

Proceedings of the 2019 International Symposium on Intelligent Signal Processing and Communication Systems, 2019

Analog / Mixed-Signal / RF Circuits for Complex Signal Processing.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Conference on ASIC, 2019

2018

A Noise Coupled ΔΣAD Modulator Using Passive Adder Embedded Noise Shaping SAR Quantizer.

[BibT_eX]

[DOI]

Chunhui Pan

Hao San

IEICE Trans. Electron., 2018

A 2nd-Order ΔΣAD Modulator Using Dynamic Analog Components with Simplified Operation Phase.

[BibT_eX]

[DOI]

Chunhui Pan

Hao San

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018

A 720µW 77.93dB SNDR ΔΣ AD Modulator Using Dynamic Analog Components With Simplified Operation Phase.

[BibT_eX]

[DOI]

Chunhui Pan

Hao San

Tsugumichi Shibata

Proceedings of the 2018 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), 2018

A 6th-Order Complex Bandpass ΔΣ AD Modulator Using Dynamic Amplifier and Noise Coupling SAR Quantizer.

[BibT_eX]

[DOI]

Chunhui Pan

Hao San

Proceedings of the 2018 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), 2018

2017

A 12-bit 1.25MS/s Area-Efficient Radix-Value Self-Estimated Non-Binary Cyclic ADC with Relaxed Requirements on Analog Components.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

A 2nd-order ΔΣAD modulator using ring amplifier and SAR quantizer with simplified operation mode.

[BibT_eX]

[DOI]

Chunhui Pan

Hao San

Tsugumichi Shibata

Proceedings of the 24th International Conference Mixed Design of Integrated Circuits and Systems, 2017

Non-binary cyclic and binary SAR hybrid ADC.

[BibT_eX]

[DOI]

Proceedings of the 24th International Conference Mixed Design of Integrated Circuits and Systems, 2017

Experimental results of reconfigurable non-binary cyclic ADC.

[BibT_eX]

[DOI]

Proceedings of the 2017 International Symposium on Intelligent Signal Processing and Communication Systems, 2017

The design of a 14-bit 400kSPS non-binary pipeline cyclic ADC.

[BibT_eX]

[DOI]

Proceedings of the 2017 International Symposium on Intelligent Signal Processing and Communication Systems, 2017

A 12-Bit 3.3MS/S pipeline cyclic ADC with correlated level shifting technique.

[BibT_eX]

[DOI]

Proceedings of the 2017 International Symposium on Intelligent Signal Processing and Communication Systems, 2017

A 14bit 80kSPS non-binary cyclic ADC without high accuracy analog components.

[BibT_eX]

[DOI]

Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

Non-binary cyclic ADC with correlated level shifting technique.

[BibT_eX]

[DOI]

Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016

A 2nd-order Delta Sigma AD modulator using dynamic amplifier and dynamic SAR quantizer.

[BibT_eX]

[DOI]

Chunhui Pan

Hao San

Tsugumichi Shibata

Proceedings of the International Symposium on Intelligent Signal Processing and Communication Systems, 2016

Leakage current compensation technique of ESD protection circuit for CMOS operational amplifier.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Intelligent Signal Processing and Communication Systems, 2016

2015

A low-distortion delta-sigma modulator with ring amplifier and passive adder embedded SAR quantizer.

[BibT_eX]

[DOI]

Chunhui Pan

Hao San

Proceedings of the 2015 International Symposium on Intelligent Signal Processing and Communication Systems, 2015

A 10-bit 10Ms/s pipeline cyclic ADC based on β-expansion.

[BibT_eX]

[DOI]

Proceedings of the 2015 International Symposium on Intelligent Signal Processing and Communication Systems, 2015

2014

Experimental Implementation of Non-binary Cyclic ADCs with Radix Value Estimation Algorithm.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2014

An area-efficient 12-bit 1.25MS/s radix-value self-estimated non-binary ADC with relaxed requirements on analog components.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2013

Robust Cyclic ADC Architecture Based on β-Expansion.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2013

Non-binary Pipeline Analog-to-Digital Converter Based on β-Expansion.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

Rigorous analysis of quantization error of an A/D converter based on β-map.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2010

Noise-Coupled Image Rejection Architecture of Complex Bandpass DeltaSigmaAD Modulator.

[BibT_eX]

[DOI]

Hao San

Haruo Kobayashi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

SAR ADC Algorithm with Redundancy and Digital Error Correction.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

Non-binary SAR ADC with digital error correction for low power applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

2009

Cross-Noise-Coupled Architecture of Complex Bandpass DeltaSigmaAD Modulator.

[BibT_eX]

[DOI]

Hao San

Haruo Kobayashi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

2008

Novel Architecture of Feedforward Second-Order Multibit Delta-Sigma-AD Modulator.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

SAR ADC algorithm with redundancy.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

High-resolution DPWM generator for digitally controlled DC-DC converters.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

ΔΣAD modulator for low power application.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007

A Second-Order Multibit Complex Bandpass DeltaSigmaAD Modulator with I, Q Dynamic Matching and DWA Algorithm.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2007

A 2.8-V Multibit Complex Bandpass Delta-Sigma-AD Modulator in 0.18µm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006

Complex Bandpass DeltaSigmaAD Modulator Architecture without I, Q-Path Crossing Layout.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

2005

Reducing Spurious Output of Balanced Modulators by Dynamic Matching of I, Q Quadrature Paths.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2005

2004

An Element Rotation Algorithm for Multi-bit DAC Nonlinearities in Complex Bandpass \Delta\SigmaAD Modulators.

[BibT_eX]

[DOI]

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

1999

A high-speed CMOS track/hold circuit.

[BibT_eX]

[DOI]

Mohd Asmawi Mohamed Zin

Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

Hao San

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