Tatsuji Matsuura
According to our database1,
Tatsuji Matsuura
authored at least 43 papers
between 1995 and 2023.
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Bibliography
2023
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., May, 2023
2021
Digital Calibration Algorithm of Conversion Error Influenced by Parasitic Capacitance in C-C SAR-ADC Based on γ-Estimation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2021
Proceedings of the International Symposium on Intelligent Signal Processing and Communication Systems, 2021
Proceedings of the International Symposium on Intelligent Signal Processing and Communication Systems, 2021
Proceedings of the International Symposium on Intelligent Signal Processing and Communication Systems, 2021
2019
Proceedings of the 2019 International Symposium on Intelligent Signal Processing and Communication Systems, 2019
Examination of Incremental ADC with SAR ADC to Reduce Conversion Time with High Accuracy.
Proceedings of the 2019 International Symposium on Intelligent Signal Processing and Communication Systems, 2019
Duty Ratio and Capacitance Analysis of AC/DC Converter without Current Control Circuit.
Proceedings of the 2019 International Symposium on Intelligent Signal Processing and Communication Systems, 2019
Investigation of Hybrid ADC Combined with First-order Feedforward Incremental and SAR ADCs.
Proceedings of the 2019 International Symposium on Intelligent Signal Processing and Communication Systems, 2019
2018
Proceedings of the 2018 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), 2018
2017
A 12-bit 1.25MS/s Area-Efficient Radix-Value Self-Estimated Non-Binary Cyclic ADC with Relaxed Requirements on Analog Components.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017
Proceedings of the 24th International Conference Mixed Design of Integrated Circuits and Systems, 2017
Proceedings of the 24th International Conference Mixed Design of Integrated Circuits and Systems, 2017
Proceedings of the 2017 International Symposium on Intelligent Signal Processing and Communication Systems, 2017
Proceedings of the 2017 International Symposium on Intelligent Signal Processing and Communication Systems, 2017
Proceedings of the 2017 International Symposium on Intelligent Signal Processing and Communication Systems, 2017
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
2016
A Replica-Amp Gain Enhancement Technique for an Operational Amplifier with Low Mismatch Sensitivity and High Voltage Swing.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016
2015
Proceedings of the 2015 International Symposium on Intelligent Signal Processing and Communication Systems, 2015
2014
A Fully Integrated SAR ADC Using Digital Correction Technique for Triple-Mode Mobile Transceiver.
IEEE J. Solid State Circuits, 2014
An area-efficient 12-bit 1.25MS/s radix-value self-estimated non-binary ADC with relaxed requirements on analog components.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014
2013
J. Electron. Test., 2013
2012
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012
2011
IEICE Trans. Electron., 2011
2010
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010
Background calibration algorithm for pipelined ADC with open-loop residue amplifier using split ADC structure.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010
2009
1-GHz Input Bandwidth Under-Sampling A/D Converter with Dynamic Current Reduction Comparator for UWB-IR Receiver.
IEICE Trans. Electron., 2009
2008
A 63 mA 112/94 dB DR IF Bandpass ΔΣ Modulator With Direct Feed-Forward Compensation and Double Sampling.
IEEE J. Solid State Circuits, 2008
2007
A Second-Order Multibit Complex Bandpass DeltaSigmaAD Modulator with I, Q Dynamic Matching and DWA Algorithm.
IEICE Trans. Electron., 2007
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
Proceedings of the 33rd European Solid-State Circuits Conference, 2007
A 63-mA 112/94-dB DR IF bandpass ΔΣ modulator with direct feed-forward and double sampling.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007
2006
Complex Bandpass DeltaSigmaAD Modulator Architecture without I, Q-Path Crossing Layout.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006
Key Technologies for Miniaturization and Power Reduction of Analog-to-Digital Converters for Video Use.
IEICE Trans. Electron., 2006
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006
1998
A 240-Mbps, 1-W CMOS EPRML read-channel LSI chip using an interleaved subranging pipeline A/D converter.
IEEE J. Solid State Circuits, 1998
1997
IEEE J. Solid State Circuits, 1997
1996
Correction to "Voltage-Comparator-Based Measurement of Equivalentiy Samlpled Substrate Noise Wavefor.
IEEE J. Solid State Circuits, 1996
Voltage-comparator-based measurement of equivalently sampled substrate noise waveforms in mixed-signal integrated circuits.
IEEE J. Solid State Circuits, 1996
1995
IEEE J. Solid State Circuits, February, 1995