Hiroshi Sakuraba

According to our database, Hiroshi Sakuraba authored at least 6 papers between 1999 and 2007.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2007

Use of Haar wavelet transform based multiple template matching for analyses of speech voice.

Shinji Karasawa, Hiroshi Sakuraba

Proceedings of the 2007 Euro American conference on Telematics and Information Systems, 2007

2006

Decananometer Surrounding Gate Transistor (SGT) Scalability by Using an Intrinsically-Doped Body and Gate Work Function Engineering.

Yasue Yamamoto, Takeshi Hidaka, Hiroki Nakamura, Hiroshi Sakuraba, Fujio Masuoka

IEICE Trans. Electron., 2006

2001

0.18- μm CMOS 10-Gb/s multiplexer/demultiplexer ICs using current mode logic with tolerance to threshold voltage fluctuation.

Akira Tanabe, Masato Umetani, Ikuo Fujiwara, Takayuki Ogura, Kotaro Kataoka, Masao Okihara, Hiroshi Sakuraba, Tetsuo Endoh, Fujio Masuoka

IEEE J. Solid State Circuits, 2001

An on-chip 96.5% current efficiency CMOS linear regulator using a flexible control technique of output current.

Tetsuo Endoh, Kazuhisa Sunaga, Hiroshi Sakuraba, Fujio Masuoka

IEEE J. Solid State Circuits, 2001

An on-chip 96.5% current efficiency CMOS linear regulator.

Kazuhisa Sunaga, Tetsuo Endoh, Hiroshi Sakuraba, Fujio Masuoka

Proceedings of ASP-DAC 2001, 2001

1999

New three-dimensional memory array architecture for future ultrahigh-density DRAM.

Tetsuo Endoh, Katsuhisa Shinmei, Hiroshi Sakuraba, Fujio Masuoka

IEEE J. Solid State Circuits, 1999