Kazuhisa Sunaga

According to our database, Kazuhisa Sunaga authored at least 5 papers between 2001 and 2010.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2010

A 16Gb/s 1^st-Tap FFE and 3-Tap DFE in 90nm CMOS.

Hideyuki Sugita, Kazuhisa Sunaga, Koichi Yamaguchi, Masayuki Mizuno

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

A 6Gb/s receiver with discrete-time based channel filtering for wireline FDM communications.

Tsutomu Takeya, Kazuhisa Sunaga, Koichi Yamaguchi, Hideyuki Sugita, Yoichi Yoshida, Masayuki Mizuno, Tadahiro Kuroda

Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009

An 18Gb/s duobinary receiver with a CDR-assisted DFE.

Kazuhisa Sunaga, Hideyuki Sugita, Koichi Yamaguchi, Kazumasa Suzuki

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2001

An on-chip 96.5% current efficiency CMOS linear regulator using a flexible control technique of output current.

Tetsuo Endoh, Kazuhisa Sunaga, Hiroshi Sakuraba, Fujio Masuoka

IEEE J. Solid State Circuits, 2001

An on-chip 96.5% current efficiency CMOS linear regulator.

Kazuhisa Sunaga, Tetsuo Endoh, Hiroshi Sakuraba, Fujio Masuoka

Proceedings of ASP-DAC 2001, 2001