Tetsuo Endoh
Orcid: 0000-0002-5583-3283
According to our database1,
Tetsuo Endoh
authored at least 73 papers
between 1993 and 2023.
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Bibliography
2023
From Algorithm to Module: Adaptive and Energy-Efficient Quantization Method for Edge Artificial Intelligence in IoT Society.
IEEE Trans. Ind. Informatics, August, 2023
Corrections to "Hybrid Signed Convolution Module With Unsigned Divide-and-Conquer Multiplier for Energy-Efficient STT-MRAM-Based AI Accelerator".
IEEE Trans. Very Large Scale Integr. Syst., June, 2023
Neuromorphic processor-oriented hybrid Q-format multiplication with adaptive quantization for tiny YOLO3.
Neural Comput. Appl., May, 2023
Hybrid Signed Convolution Module With Unsigned Divide-and-Conquer Multiplier for Energy-Efficient STT-MRAM-Based AI Accelerator.
IEEE Trans. Very Large Scale Integr. Syst., 2023
2022
Energy-Efficient Convolution Module With Flexible Bit-Adjustment Method and ADC Multiplier Architecture for Industrial IoT.
IEEE Trans. Ind. Informatics, 2022
Design and Heavy-Ion Testing of MTJ/CMOS Hybrid LSIs for Space-Grade Soft-Error Reliability.
Proceedings of the IEEE International Reliability Physics Symposium, 2022
2021
Dual-Port SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations Under Field-Assistance-Free Condition.
IEEE J. Solid State Circuits, 2021
2020
FPGA Implementation of Real-Time Pedestrian Detection Using Normalization-Based Validation of Adaptive Features Clustering.
IEEE Trans. Veh. Technol., 2020
A Systematic Study of Tiny YOLO3 Inference: Toward Compact Brainware Processor With Less Memory and Logic Gate.
IEEE Access, 2020
Normalization-Based Validity Index of Adaptive K-Means Clustering for Multi-Solution Application.
IEEE Access, 2020
Dual-Port Field-Free SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations under 55-nm CMOS Technology and 1.2-V Supply Voltage.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
2019
A 47.14-µW 200-MHz MOS/MTJ-Hybrid Nonvolatile Microcontroller Unit Embedding STT-MRAM and FPGA for IoT Applications.
IEEE J. Solid State Circuits, 2019
Proceedings of the 19th Non-Volatile Memory Technology Symposium, 2019
An FPGA-Accelerated Fully Nonvolatile Microcontroller Unit for Sensor-Node Applications in 40nm CMOS/MTJ-Hybrid Technology Achieving 47.14μW Operation at 200MHz.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
2018
Accurate error bit mode analysis of STT-MRAM chip with a novel current measurement module implemented to gigabit class memory test system.
Proceedings of the Non-Volatile Memory Technology Symposium, 2018
2017
Embedded nonvolatile memory with STT-MRAMs and its application for nonvolatile brain-inspired VLSIs.
Proceedings of the 2017 International Symposium on VLSI Design, Automation and Test, 2017
2016
Proc. IEEE, 2016
Formation mechanism of concave by dielectric breakdown on silicon carbide metal-oxide-semiconductor capacitor.
Microelectron. Reliab., 2016
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016
Stochastic behavior-considered VLSI CAD environment for MTJ/MOS-hybrid microprocessor design.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
2015
Nonvolatile Logic-in-Memory LSI Using Cycle-Based Power Gating and its Application to Motion-Vector Prediction.
IEEE J. Solid State Circuits, 2015
Fabrication of a 3000-6-input-LUTs embedded and block-level power-gated nonvolatile FPGA chip using p-MTJ-based logic-in-memory structure.
Proceedings of the Symposium on VLSI Circuits, 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
2014
A High Output Resistance 1.2-V VDD Current Mirror with Deep Submicron Vertical MOSFETs.
IEICE Trans. Electron., 2014
A Novel Alternating Voltage Controlled Current Sensing Method for Suppressing Thermal Dependency.
IEICE Trans. Electron., 2014
A compact low-power nonvolatile flip-flop using domain-wall-motion-device-based single-ended structure.
IEICE Electron. Express, 2014
Complementary 5T-4MTJ nonvolatile TCAM cell circuit with phase-selective parallel writing scheme.
IEICE Electron. Express, 2014
Design of an energy-efficient 2T-2MTJ nonvolatile TCAM based on a parallel-serial-combined search scheme.
IEICE Electron. Express, 2014
A Nonvolatile Associative Memory-Based Context-Driven Search Engine Using 90 nm CMOS/MTJ-Hybrid Logic-in-Memory Architecture.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2014
10.5 A 90nm 20MHz fully nonvolatile microcontroller for standby-power-critical applications.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
A delay circuit with 4-terminal magnetic-random-access-memory device for power-efficient time- domain signal processing.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
2013
IEICE Trans. Electron., 2013
Fabrication of a magnetic tunnel junction-based 240-tile nonvolatile field-programmable gate array chip skipping wasted write operations for greedy power-reduced logic applications.
IEICE Electron. Express, 2013
Nonvolatile logic-in-memory array processor in 90nm MTJ/MOS achieving 75% leakage reduction using cycle-based power gating.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
An MTJ-based nonvolatile associative memory architecture with intelligent power-saving scheme for high-speed low-power recognition applications.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
2012
IEICE Trans. Electron., 2012
FG Width Scalability of the 3-D Vertical FG NAND Using the Sidewall Control Gate (SCG).
IEICE Trans. Electron., 2012
IEICE Trans. Electron., 2012
Current Controlled MOS Current Mode Logic with Auto-Detection of Threshold Voltage Fluctuation.
IEICE Trans. Electron., 2012
IEICE Trans. Electron., 2012
1Mb 4T-2MTJ nonvolatile STT-RAM for embedded memories using 32b fine-grained power gating technique with 1.0ns/200ps wake-up/power-off times.
Proceedings of the Symposium on VLSI Circuits, 2012
A 3.14 um<sup>2</sup> 4T-2MTJ-cell fully parallel TCAM based on nonvolatile logic-in-memory architecture.
Proceedings of the Symposium on VLSI Circuits, 2012
High-speed simulator including accurate MTJ models for spintronics integrated circuit design.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Implementation of a perpendicular MTJ-based read-disturb-tolerant 2T-2R nonvolatile TCAM based on a reversed current reading scheme.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012
2011
The Optimum Physical Targets of the 3-Dimensional Vertical FG NAND Flash Memory Cell Arrays with the Extended Sidewall Control Gate (ESCG) Structure.
IEICE Trans. Electron., 2011
Temperature Dependency of Driving Current in High-k/Metal Gate MOSFET and Its Influence on CMOS Inverter Circuit.
IEICE Trans. Electron., 2011
IEICE Trans. Electron., 2011
IEICE Trans. Electron., 2011
IEICE Trans. Electron., 2011
Verification of Stable Circuit Operation of 180 nm Current Controlled MOS Current Mode Logic under Threshold Voltage Fluctuation.
IEICE Trans. Electron., 2011
Evaluation of 1/f Noise Characteristics in High-k/Metal Gate and SiON/Poly-Si Gate MOSFET with 65 nm CMOS Process.
IEICE Trans. Electron., 2011
The Impact of Current Controlled-MOS Current Mode Logic/Magnetic Tunnel Junction Hybrid Circuit for Stable and High-Speed Operation.
IEICE Trans. Electron., 2011
A vertical-MOSFET-based digital core circuit for high-speed low-power vector matching.
Proceedings of the International SoC Design Conference, 2011
2010
Importance of the Electronic State on the Electrode in Electron Tunneling Processes between the Electrode and the Quantum Dot.
IEICE Trans. Electron., 2010
Transient Characteristic of Fabricated Magnetic Tunnel Junction (MTJ) Programmed with CMOS Circuit.
IEICE Trans. Electron., 2010
Study of the DC Performance of Fabricated Magnetic Tunnel Junction Integrated on Back-End Metal Line of CMOS Circuits.
IEICE Trans. Electron., 2010
IEICE Trans. Electron., 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
2009
IEICE Trans. Electron., 2009
IEICE Trans. Electron., 2009
Novel Concept Dynamic Feedback MCML Technique for High-Speed and High-Gain MCML Type Latch.
IEICE Trans. Electron., 2009
Proceedings of the Design, Automation and Test in Europe, 2009
2007
Study of 30-nm Double-Gate MOSFET with Halo Implantation Technology Using a Two-Dimensional Device Simulator.
IEICE Trans. Electron., 2007
Physical Origin of Stress-Induced Leakage Currents in Ultra-Thin Silicon Dioxide Films.
IEICE Trans. Electron., 2007
2001
0.18- μm CMOS 10-Gb/s multiplexer/demultiplexer ICs using current mode logic with tolerance to threshold voltage fluctuation.
IEEE J. Solid State Circuits, 2001
An on-chip 96.5% current efficiency CMOS linear regulator using a flexible control technique of output current.
IEEE J. Solid State Circuits, 2001
Proceedings of ASP-DAC 2001, 2001
1999
IEEE J. Solid State Circuits, 1999
1993