Hongbing Fan

Ray C. C. Cheung

Comput. J., 2013

2012

R-NoC: An Efficient Packet-Switched Reconfigurable Networks-on-Chip.

[BibT_eX]

[DOI]

Yue-Ang Chen

Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2012

2011

On Structural Analysis and Efficiency for Graph-Based Rewiring Techniques.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011

2010

Structured Overlay Network for File Distribution.

[BibT_eX]

[DOI]

Proceedings of the Combinatorial Optimization and Applications, 2010

Design Automation for Reconfigurable Interconnection Networks.

[BibT_eX]

[DOI]

Chak-Chung Cheung

Proceedings of the Reconfigurable Computing: Architectures, 2010

2009

A New Approach for Rearrangeable Multicast Switching Networks.

[BibT_eX]

[DOI]

Proceedings of the Combinatorial Optimization and Applications, 2009

2008

Customized Reconfigurable Interconnection Networks for multiple application SOCS.

[BibT_eX]

[DOI]

Jason Ernst

Proceedings of the FPL 2008, 2008

Interconnection Graph Problem.

[BibT_eX]

Proceedings of the 2008 International Conference on Foundations of Computer Science, 2008

Algorithms and Implementation for Interconnection Graph Problem.

[BibT_eX]

[DOI]

Proceedings of the Combinatorial Optimization and Applications, 2008

2007

The exact channel density and compound design for generic universal switch blocks.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2007

2006

Decomposition Design Theory and Methodology for Arbitrary-Shaped Switch Boxes.

[BibT_eX]

[DOI]

Ray Chak-Chung Cheung

IEEE Trans. Computers, 2006

An Edge Ordering Problem of Regular Hypergraphs.

[BibT_eX]

[DOI]

Robert Kalbfleisch

Proceedings of the Computing and Combinatorics, 12th Annual International Conference, 2006

2005

A refined search tree technique for Dominating Set on planar graphs.

[BibT_eX]

[DOI]

J. Comput. Syst. Sci., 2005

Crossbar based design schemes for switch boxes and programmable interconnection networks.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

The dominating set problem is fixed parameter tractable for graphs of bounded genus.

[BibT_eX]

[DOI]

John A. Ellis

Michael R. Fellows

J. Algorithms, 2004

On Optimal Irregular Switch Box Designs.

[BibT_eX]

[DOI]

Proceedings of the Field Programmable Logic and Application, 2004

2003

A combinatorial switch block design technique for reconfigurable interconnection networks.

[BibT_eX]

[DOI]

PhD thesis, 2003

Further improve circuit partitioning using GBAW logic perturbation techniques.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2003

On optimal hyperuniversal and rearrangeable switch box designs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

General Models and a Reduction Design Technique for FPGA Switch Box Designs.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2003

An Efficient Exact Router for Hyper-Universal Switching Box.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003

On improving FPGA routability applying multi-level switch boxes.

[BibT_eX]

[DOI]

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002

Reduction design for generic universal switch blocks.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2002

Comment on Generic Universal Switch Blocks.

[BibT_eX]

[DOI]

Yao-Wen Chang

IEEE Trans. Computers, 2002

The Cycles of the Multiway Perfect Shuffle Permutation.

[BibT_eX]

[DOI]

John A. Ellis

Jeffrey O. Shallit

Discret. Math. Theor. Comput. Sci., 2002

On Optimum Designs of Universal Switch Blocks.

[BibT_eX]

[DOI]

Proceedings of the Field-Programmable Logic and Applications, 2002

2001

On Fixed Edges and Edge-Reconstruction of Series-Parallel Networks.

[BibT_eX]

[DOI]

C. K. Wong

Graphs Comb., 2001

On Optimum Switch Box Designs for 2-D FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 38th Design Automation Conference, 2001

Combinatorial routing analysis and design of universal switch blocks.

[BibT_eX]

[DOI]

Proceedings of ASP-DAC 2001, 2001

2000

OBDD Minimization Based on Two-Level Representation of Boolean Functions.

[BibT_eX]

[DOI]

Malgorzata Marek-Sadowska

C. K. Wong

IEEE Trans. Computers, 2000

Computing the cycles in the perfect shuffle permutation.

[BibT_eX]

[DOI]

John A. Ellis

Tobias Krahn

Inf. Process. Lett., 2000

A Fast Graph-Based Alternative Wiring Scheme for Boolean Networks.

[BibT_eX]

[DOI]

Wangning Long

Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

On improved graph-based alternative wiring scheme for multi-level logic optimization.

[BibT_eX]

[DOI]

Proceedings of the 2000 7th IEEE International Conference on Electronics, 2000

A global routing model for universal switch box design.

[BibT_eX]

[DOI]

Proceedings of the 2000 7th IEEE International Conference on Electronics, 2000

General Models for Optimum Arbitrary-Dimension FPGA Switch Box Designs.

[BibT_eX]

[DOI]

Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

1998

Oriented walk double covering and bidirectional double tracing.

[BibT_eX]

[DOI]

Xuding Zhu

J. Graph Theory, 1998

On thin Boolean functions and related optimum OBDD ordering.

[BibT_eX]

[DOI]

C. K. Wong

Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998

1996

On the fixed edge of planar graphs with minimum degree five.

[BibT_eX]

[DOI]

Baogang Xu