Yu-Liang Wu
Orcid: 0000-0002-5181-056XAffiliations:
- Chinese University of Hong Kong
According to our database1,
Yu-Liang Wu
authored at least 85 papers
between 1993 and 2023.
Collaborative distances:
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Bibliography
2023
Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2023
2022
Theor. Comput. Sci., 2022
2018
Motion Resistant Image-Photoplethysmography Based on Spectral Peak Tracking Algorithm.
IEEE Access, 2018
2016
To Detect, Locate, and Mask Hardware Trojans in digital circuits by reverse engineering and functional ECO.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
Coupling reverse engineering and SAT to tackle NP-complete arithmetic circuitry verification in ∼O(# of gates).
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
2014
Proceedings of the 2014 27th International Conference on VLSI Design, 2014
On macro-fault: a new fault model, its implications on fault tolerance and manufacturing yield.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014
2013
Comput. J., 2013
A cross-layer fault-tolerant design method for high manufacturing yield and system reliability.
Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013
Mountain-mover: An intuitive logic shifting heuristic for improving timing slack violating paths.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
2012
ACM Trans. Design Autom. Electr. Syst., 2012
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012
Almost every wire is removable: A modeling and solution for removing any circuit wire.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
ECO timing optimization with negotiation-based re-routing and logic re-structuring using spare cells.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2012
2011
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011
Proceedings of the 12th International Conference on Computer-Aided Design and Computer Graphics, 2011
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011
2010
Improving redundancy addition and removal using unreachable states for sequential circuits.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010
Proceedings of the 47th Design Automation Conference, 2010
Proceedings of the Combinatorial Optimization and Applications, 2010
Proceedings of the Reconfigurable Computing: Architectures, 2010
2009
Proceedings of the Combinatorial Optimization and Applications, 2009
2008
The Vertex Linear Arboricity of Claw-Free Graphs with Small Degree.
Ars Comb., 2008
Proceedings of the FPL 2008, 2008
Interconnection Graph Problem.
Proceedings of the 2008 International Conference on Foundations of Computer Science, 2008
A Quantitative Study of the Routing Architecture Exploring Routing Locality Property for Better Performance and Routability.
Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2008
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008
Proceedings of the Combinatorial Optimization and Applications, 2008
Proceedings of the Technological Developments in Education and Automation, 2008
2007
ACM Trans. Design Autom. Electr. Syst., 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the 44th Design Automation Conference, 2007
2006
IEEE Trans. Computers, 2006
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006
2005
IEEE Trans. Instrum. Meas., 2005
On Improved Least Flexibility First Heuristics Superior for Packing and Stock Cutting Problems.
Proceedings of the Stochastic Algorithms: Foundations and Applications, 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005
Crossbar based design schemes for switch boxes and programmable interconnection networks.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
2004
Proceedings of the Operations Research, 2004
Proceedings of the Field Programmable Logic and Application, 2004
Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004
2003
IEEE Trans. Very Large Scale Integr. Syst., 2003
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003
IEEE Trans. Computers, 2003
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003
A cost-effective scan architecture for scan testing with non-scan test power and test application cost.
Proceedings of the 40th Design Automation Conference, 2003
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003
2002
ACM Trans. Design Autom. Electr. Syst., 2002
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002
Eur. J. Oper. Res., 2002
Proceedings of the Field-Programmable Logic and Applications, 2002
2001
Graphs Comb., 2001
Proceedings of the Conference on Design, Automation and Test in Europe, 2001
Proceedings of the 38th Design Automation Conference, 2001
Proceedings of ASP-DAC 2001, 2001
Proceedings of ASP-DAC 2001, 2001
2000
IEEE Trans. Computers, 2000
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000
On improved graph-based alternative wiring scheme for multi-level logic optimization.
Proceedings of the 2000 7th IEEE International Conference on Electronics, 2000
Proceedings of the 2000 7th IEEE International Conference on Electronics, 2000
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000
Proceedings of ASP-DAC 2000, 2000
Proceedings of ASP-DAC 2000, 2000
1999
On the Testing Quality of Random and Pseudo-random Sequences for Permanent and Intermittent Faults.
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999
Proceedings of the Handbook of Combinatorial Optimization, 1999
1998
On the optimal four-way switch box routing structures of FPGA greedy routing architectures1.
Integr., 1998
A tree-structured LFSR synthesis scheme for pseudo-exhaustive testing of VLSI circuits.
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998
Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998
Proceedings of the ASP-DAC '98, 1998
1997
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997
1996
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996
1995
Proceedings of the 32st Conference on Design Automation, 1995
Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995
1994
On the NP-completeness of regular 2-D FPGA routing architectures and a novel solution.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994
Proceedings of the Fourth Great Lakes Symposium on Design Automation of High Performance VLSI Systems, 1994
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994
1993
Proceedings of the European Design Automation Conference 1993, 1993