Cliff C. N. Sze

According to our database1, Cliff C. N. Sze authored at least 64 papers between 2000 and 2017.

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Bibliography

2017
Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration.
IPSJ Trans. Syst. LSI Des. Methodol., 2017

Fast and Highly Scalable Bayesian MDP on a GPU Platform.
Proceedings of the 8th ACM International Conference on Bioinformatics, 2017

2016
Challenges of cell selection algorithms in industrial high performance microprocessor designs.
Integr., 2016

Cell Selection for High-Performance Designs in an Industrial Design Flow.
Proceedings of the 2016 on International Symposium on Physical Design, 2016

GPU acceleration for Bayesian control of Markovian genetic regulatory networks.
Proceedings of the 2016 IEEE-EMBS International Conference on Biomedical and Health Informatics, 2016

2015
Obstacle-Avoiding and Slew-Constrained Clock Tree Synthesis With Efficient Buffer Insertion.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Guest Editorial: Special Section on Physical Design Techniques for Advanced Technology Nodes.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Gate sizing and threshold voltage assignment for high performance microprocessor designs.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
Techniques for scalable and effective routability evaluation.
ACM Trans. Design Autom. Electr. Syst., 2014

Guest Editorial Special Section on Contemporary and Emerging Issues in Physical Design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Pacman: driving nonuniform clock grid loads for low-skew robust clock network.
Proceedings of the ACM/IEEE International Workshop on System Level Interconnect Prediction, 2014

2013
ISPD 2013 expert designer/user session (eds).
Proceedings of the International Symposium on Physical Design, 2013

Clock power minimization using structured latch templates and decision tree induction.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Hardware Acceleration of an Efficient and Accurate Proton Therapy Monte Carlo.
Proceedings of the International Conference on Computational Science, 2013

CATALYST: planning layer directives for effective design closure.
Proceedings of the Design, Automation and Test in Europe, 2013

Routing congestion estimation with real design constraints.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Mountain-mover: An intuitive logic shifting heuristic for improving timing slack violating paths.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012
Postgrid Clock Routing for High Performance Microprocessor Designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

ICCAD-2012 CAD contest in design hierarchy aware routability-driven placement and benchmark suite.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

Placement: Hot or Not?
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

WRIP: logic restructuring techniques for wirelength-driven incremental placement.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

GLARE: global and local wiring aware routability evaluation.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

The DAC 2012 routability-driven placement contest and benchmark suite.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Guiding a physical design closure system to produce easier-to-route designs with more predictable timing.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011
Shedding Physical Synthesis Area Bloat.
VLSI Design, 2011

Physical Synthesis with Clock-Network Optimization for Large Systems on Chips.
IEEE Micro, 2011

Design methodology for the IBM POWER7 microprocessor.
IBM J. Res. Dev., 2011

Quantifying academic placer performance on custom designs.
Proceedings of the 2011 International Symposium on Physical Design, 2011

The ISPD-2011 routability-driven placement contest and benchmark suite.
Proceedings of the 2011 International Symposium on Physical Design, 2011

Grid-to-ports clock routing for high performance microprocessor designs.
Proceedings of the 2011 International Symposium on Physical Design, 2011

The future of clock network synthesis.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Obstacle-avoiding and slew-constrained buffered clock tree synthesis for skew optimization.
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

Wire synthesizable global routing for timing closure.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010
ISPD 2010 high performance clock network synthesis contest: benchmark suite and results.
Proceedings of the 2010 International Symposium on Physical Design, 2010

Ultra-fast interconnect driven cell cloning for minimizing critical path delay.
Proceedings of the 2010 International Symposium on Physical Design, 2010

A methodology for propagating design tolerances to shape tolerances for use in manufacturing.
Proceedings of the Design, Automation and Test in Europe, 2010

2009
Ispd2009 clock network synthesis contest.
Proceedings of the 2009 International Symposium on Physical Design, 2009

2008
Buffering in the Layout Environment.
Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008

Timing-Driven Interconnect Synthesis.
Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008

RUMBLE: An Incremental Timing-Driven Physical-Synthesis Optimization Algorithm.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

The ISPD global routing benchmark suite.
Proceedings of the 2008 International Symposium on Physical Design, 2008

Pyramids: an efficient computational geometry-based approach for timing-driven placement.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

2007
Algorithms for the scaling toward nanometer VLSI physical synthesis.
PhD thesis, 2007

Path-Based Buffer Insertion.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Fast Algorithms for Slew-Constrained Minimum Cost Buffering.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Techniques for Fast Physical Synthesis.
Proc. IEEE, 2007

The nuts and bolts of physical synthesis.
Proceedings of the Ninth International Workshop on System-Level Interconnect Prediction (SLIP 2007), 2007

2006
Accurate estimation of global buffer delay within a floorplan.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Integrated placement and skew optimization for rotary clocking.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Timing-driven Steiner trees are (practically) free.
Proceedings of the 43rd Design Automation Conference, 2006

2005
Navigating Register Placement for Low Power Clock Network Design.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

Navigating registers in placement for clock network minimization.
Proceedings of the 42nd Design Automation Conference, 2005

Skew scheduling and clock routing for improved tolerance to process variations.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Register placement for low power clock network.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Making fast buffer insertion even faster via approximation techniques.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
Multilevel circuit clustering for delay minimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Porosity-aware buffered Steiner tree construction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

A place and route aware buffered Steiner tree construction.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003
Optimal circuit clustering for delay minimization under a more general delay model.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Performance-driven multi-level clustering for combinational circuits.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002
Multi-Level Circuit Clustering for Delay Minimization.
Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002

Optimal circuit clustering with variable interconnect delay.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

2001
Improved alternative wiring scheme applying dominator relationship.
Proceedings of ASP-DAC 2001, 2001

2000
On improved graph-based alternative wiring scheme for multi-level logic optimization.
Proceedings of the 2000 7th IEEE International Conference on Electronics, 2000


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