How-Rern Lin

According to our database, How-Rern Lin authored at least 8 papers between 1994 and 2010.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2010

Combined Use of Rising and Falling Edge Triggered Clocks for Peak Current Reduction in IP-Based SoC/NoC Designs.

Tsung-Yi Wu, Tzi-Wei Kao, How-Rern Lin

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

Combined use of rising and falling edge triggered clocks for peak current reduction in IP-based SoC designs.

Tsung-Yi Wu, Tzi-Wei Kao, Shi-Yi Huang, Tai-Lun Li, How-Rern Lin

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009

A Conditional Isolation Technique for Low-Energy and High-Performance Wide Domino Gates.

How-Rern Lin, Wei-Hao Chiu, Tsung-Yi Wu

IEICE Trans. Electron., 2009

1999

On determining sensitization criterion in an iterative gate sizing process.

How-Rern Lin, TingTing Hwang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

1996

Cell height driven transistor sizing in a cell based static CMOS module design.

How-Rern Lin, Yu-Chin Hsu, TingTing Hwang

IEEE J. Solid State Circuits, 1996

1995

Power recduction by gate sizing with path-oriented slack calculation.

How-Rern Lin, TingTing Hwang

Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995

1994

Dynamical identification of critical paths for iterative gate sizing.

How-Rern Lin, TingTing Hwang

Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

Cell Height Driven Transistor Sizing in a Cell Based Module Design.

How-Rern Lin, Ching-Lung Chou, Yu-Chin Hsu, TingTing Hwang

Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994