Wei-Hao Chiu

According to our database1, Wei-Hao Chiu authored at least 8 papers between 2009 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2020


2012
Low-complexity architecture of carrier frequency offset estimation and compensation for body area network systems.
Comput. Math. Appl., 2012

2011
A Synchronous 50% Duty-Cycle Clock Generator in 0.35- μ m CMOS.
IEEE Trans. Very Large Scale Integr. Syst., 2011

A 4MHz BW 69dB SNDR continuous-time delta-sigma modulator with reduced sensitivity to clock jitter.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

2010
A Dynamic Phase Error Compensation Technique for Fast-Locking Phase-Locked Loops.
IEEE J. Solid State Circuits, 2010

A 5-GHz fractional-N phase-locked loop with spur reduction technique in 0.13-μm CMOS.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009
A Conditional Isolation Technique for Low-Energy and High-Performance Wide Domino Gates.
IEICE Trans. Electron., 2009


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