Yu-Chin Hsu

According to our database1, Yu-Chin Hsu authored at least 53 papers between 1987 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

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Bibliography

2020
Intelligent Chips and Technologies for AIoT Era.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2020

2018
Risk assessment in new software development projects at the front end: a fuzzy logic approach.
J. Ambient Intell. Humaniz. Comput., 2018

2016
Towards Understanding Senior Citizens' Gateball Participations Behavior and Well-Being: An Application of the Theory of Planned Behavior.
Proceedings of the Human Interface and the Management of Information: Applications and Services, 2016

2012
Identifying ill tool combinations via Gibbs sampler for semiconductor manufacturing yield diagnosis.
Proceedings of the Winter Simulation Conference, 2012

2011
A method to leverage pre-silicon collateral and analysis for post-silicon testing and validation.
Proceedings of the 48th Design Automation Conference, 2011

2008
A General Failure Candidate Ranking Framework for Silicon Debug.
Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

2007
Bridging RTL and gate: correlating different levels of abstraction for design debugging.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2007

2006
Diagnosing Silicon Failures Based on Functional Test Patterns.
Proceedings of the Seventh International Workshop on Microprocessor Test and Verification (MTV 2006), 2006

Visibility enhancement for silicon debug.
Proceedings of the 43rd Design Automation Conference, 2006

2003
Advanced techniques for RTL debugging.
Proceedings of the 40th Design Automation Conference, 2003

2002
Optimal time borrowing analysis and timing budgeting optimization for latch-based designs.
ACM Trans. Design Autom. Electr. Syst., 2002

2000
Timing optimization on routed designs with incremental placementand routing characterization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

1999
Post-routing timing optimization with routing characterization.
Proceedings of the 1999 International Symposium on Physical Design, 1999

FSMD Functional Partitioning for Low Power.
Proceedings of the 1999 Design, 1999

1998
Functional partitioning improvements over structural partitioning for packaging constraints and synthesis: tool performance.
ACM Trans. Design Autom. Electr. Syst., 1998

Eliminating false loops caused by sharing in control path.
ACM Trans. Design Autom. Electr. Syst., 1998

1997
Layout Modeling and Design Space Exploration in Pss1 System.
VLSI Design, 1997

Domain-Specific High-Level Modeling and Synthesis for ATM Switch Prototyping.
Des. Autom. Embed. Syst., 1997

On the control-subroutine implementation of subprogram synthesis.
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

1996
Cell height driven transistor sizing in a cell based static CMOS module design.
IEEE J. Solid State Circuits, 1996

A Comparison of Functional and Structural Partitioning.
Proceedings of the 9th International Symposium on System Synthesis, 1996

Domain-Specific High-Level Modeling and Synthesis for ATM Switch Design Using VHDL.
Proceedings of the 33st Conference on Design Automation, 1996

1995
A new scheduling algorithm for synthesizing the control blocks of control-dominated circuits.
Microprocess. Microprogramming, 1995

A new approach to schedule operations across nested-ifs and nested-loops.
Microprocess. Microprogramming, 1995

Synthesis of false loop free circuits.
Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995

1994
MULTIPAR: behavioral partition for synthesizing multiprocessor architectures.
IEEE Trans. Very Large Scale Integr. Syst., 1994

Rectilinear Steiner tree construction by local and global refinement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

Cell Height Driven Transistor Sizing in a Cell Based Module Design.
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

1993
An efficient layout style for two-metal CMOS leaf cells and its automatic synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

PLS: a scheduler for pipeline synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

Zone scheduling.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

High throughput pipelined data path synthesis by conserving the regularity of nested loops.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

1992
STAR: An automatic data path allocator.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

Zero Skew Clock Net Routing.
Proceedings of the 29th Design Automation Conference, 1992

1991
A formal approach to the scheduling problem in high level synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

LiB: a CMOS cell compiler.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

Combining Logic Minimization and Folding for PLA's.
IEEE Trans. Computers, 1991

Efficient Microcode Arrangement and Controller Synthesis for Application Specific Integrated Circuits.
Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

An Efficient Layout Style for 2-Metal CMOS Leaf Cells And Their Automatic Generation.
Proceedings of the 28th Design Automation Conference, 1991

Scheduling for Functional Pipelining and Loop Winding.
Proceedings of the 28th Design Automation Conference, 1991

1990
Hybrid routing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990

A fast transistor-chaining algorithm for CMOS cell layout.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990

A new algorithm for tile generation.
Integr., 1990

Data Path Construction and Refinement.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

Optimum and Heuristic Data Path Scheduling Under Resource Constraints.
Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

Data Path Allocation Based on Bipartite Weighted Matching.
Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

LiB: A Cell Layout Generator.
Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

1989
SILK: a simulated evolution router.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989

Routing using a pyramid data structure.
Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

A new integer linear programming formulation for the scheduling problem in data path synthesis.
Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

An optimal transistor-chaining algorithm for CMOS cell layout.
Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

1988
A detailed router based on simulated evolution.
Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988

1987
Floor Planning and Global Routing in an Automated Chip Design System
PhD thesis, 1987


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