Hsin-Shu Chen

Orcid: 0000-0002-7666-4984

According to our database1, Hsin-Shu Chen authored at least 30 papers between 1999 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
A Highly Multi-Bit Continuous-Time Delta-Sigma Modulator ADC with 9-Bit Feedback.
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

2022
A PVT-Invariant Front-End Ring Amplifier using Self-Stabilization Technique for SAR ADC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021
Reconfigurable Switched-Capacitor DC-DC Converter with Adaptive Switch Modulation and Frequency Scaling Techniques.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020
A 6b 1GS/s 2b/Cycle SAR ADC with Body-Voltage Offset Calibration.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019
A 0.6 V 1.63 fJ/c.-s. Detective Open-Loop Dynamic System Buffer for SAR ADC in Zero-Capacitor TDDI System.
IEEE J. Solid State Circuits, 2019

A Fast-Transient Switched-Capacitor DC-DC Converter with a Current Sensing Control Technique.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

2018
A 0.25μm HV-CMOS Synchronous Inversion and Charge Extraction (SICE) Interface Circuit for Piezoelectric Energy Harvesting.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

An 89.55dB-SFDR 179.6dB-FoMs 12-bit lMS/s SAR-Assisted SAR ADC with Weight-Split Compensation Calibration.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

A 0.6V 1.63fJ/c.-s. Detective Open-Loop Dynamic System Buffer for SAR ADC in Zero-Capacitor TDDI System.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

2017
A current average control method for transient-glitch reduction in variable frequency DC-DC converters.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016
An 8 b 700 MS/s 1 b/Cycle SAR ADC Using a Delay-Shift Technique.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

A 12.5-fJ/Conversion-Step 8-Bit 800-MS/s Two-Step SAR ADC.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

An 8-bit 900MS/S two-step SAR ADC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

A 12-bit 200kS/s subranging SAR ADC with an energy-curve reshape technique.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

A 0.9V 15fJ/conversion-step 8-bit 1.5GS/s two-step SAR ADC.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2014
A 6-Bit 1 GS/s Pipeline ADC Using Incomplete Settling With Background Sampling-Point Calibration.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

A 6-bit 1-GS/s Two-Step SAR ADC in 40-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2014

11.2 A 0.85fJ/conversion-step 10b 200kS/s subranging SAR ADC in 40nm CMOS.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

A 0.6V 6.4fJ/conversion-step 10-bit 150MS/s subranging SAR ADC in 40nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

2013
A 10-Bit 200 MS/s Capacitor-Sharing Pipeline ADC.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

2012
A High-Efficiency CMOS DC-DC Converter With 9-µs Transient Recovery Time.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012

A 10-b 320-MS/s Stage-Gain-Error Self-Calibration Pipeline ADC.
IEEE J. Solid State Circuits, 2012

A 3.2fJ/c.-s. 0.35V 10b 100KS/s SAR ADC in 90nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2012

A highly integrated class-D amplifier using driver delay hysteresis control.
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012

2010
A Fast-Lock Low-Power Subranging Digital Delay-Locked Loop.
IEICE Trans. Electron., 2010

2009
A 1-GS/s 6-Bit Two-Channel Two-Step ADC in 0.13-µm CMOS.
IEEE J. Solid State Circuits, 2009

2006
A 1.5-V 10-ppm/°C 2nd-order curvature-compensated CMOS bandgap reference with trimming.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2001
High-Resolution Nyquist -Rate Analog -to -Digital Converter
PhD thesis, 2001

A 14-b 20-Msamples/s CMOS pipelined ADC.
IEEE J. Solid State Circuits, 2001

1999
Characterization of 1/f noise vs. number of gate stripes in MOS transistors.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999


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