Bang-Sup Song

Affiliations:
  • University of California, San Diego, USA


According to our database1, Bang-Sup Song authored at least 41 papers between 1993 and 2014.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Awards

IEEE Fellow

IEEE Fellow 1999, "For contributions to integrated filters and analog-digital converters.".

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2014
A 14b 60 MS/s Pipelined ADC Adaptively Cancelling Opamp Gain and Nonlinearity.
IEEE J. Solid State Circuits, 2014

2013
Adaptive cancellation of gain and nonlinearity errors in pipelined ADCs.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2010
LMS-Based Noise Leakage Calibration of Cascaded Continuous-Time Delta Sigma Modulators.
IEEE J. Solid State Circuits, 2010

2009
A 10∼15-bit 60-MS/s Floating-Point ADC With Digital Gain and Offset Calibration.
IEEE J. Solid State Circuits, 2009

A Fifth-Order G<sub>m</sub>-C Continuous-Time ΔΣ Modulator With Process-Insensitive Input Linear Range.
IEEE J. Solid State Circuits, 2009

A self-calibrated 2-1-1 cascaded continuous-time ΔΣ modulator.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

2008
A 15-bit Linear 20-MS/s Pipelined ADC Digitally Calibrated With Signal-Dependent Dithering.
IEEE J. Solid State Circuits, 2008

A 48-860 MHz CMOS Low-IF Direct-Conversion DTV Tuner.
IEEE J. Solid State Circuits, 2008

A 65nm CMOS CT ΔΣ Modulator with 81dB DR and 8MHz BW Auto-Tuned by Pulse Injection.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

A 10∼15b 60MS/s floating-point ADC with digital gain and offset calibration.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007
A 10-bit 50-MS/s Pipelined ADC With Opamp Current Reuse.
IEEE J. Solid State Circuits, 2007

A 13-b Linear, 40-MS/s Pipelined ADC With Self-Configured Capacitor Matching.
IEEE J. Solid State Circuits, 2007

A 48-to-860MHz CMOS Direct-Conversion TV Tuner.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2006
A Complex Image Rejection Circuit With Sign Detection Only.
IEEE J. Solid State Circuits, 2006

A CMOS 1×-16× speed DVD write channel IC.
IEEE J. Solid State Circuits, 2006

A 1.8-GHz Spur-Cancelled Fractional-N Frequency Synthesizer With LMS-Based DAC Gain Calibration.
IEEE J. Solid State Circuits, 2006

A 10b 50MS/s pipelined ADC with opamp current reuse.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

A 13b linear 40MS/s pipelined ADC with self-configured capacitor matching.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

A 1.8GHz Spur-Cancelled Fractional-N Frequency Synthesizer with LMS-Based DAC Gain Calibration.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2005
A CMOS TV tuner/demodulator IC with digital image rejection.
IEEE J. Solid State Circuits, 2005

2004
A 14-b linear capacitor self-trimming pipelined ADC.
IEEE J. Solid State Circuits, 2004

A 2.4-GHz dual-mode 0.18-μm CMOS transceiver for Bluetooth and 802.11b.
IEEE J. Solid State Circuits, 2004

2003
Correction to "A carry-free 54 b x 54 b multiplier using equivalent bit conversion algorithm".
IEEE J. Solid State Circuits, 2003

A 1.8-GHz CMOS fractional-N frequency synthesizer with randomized multiphase VCO.
IEEE J. Solid State Circuits, 2003

Comments on "A carry-free 54 b×54 b multiplier using equivalent bit conversion algorithm".
IEEE J. Solid State Circuits, 2003

2001
A carry-free 54b×54b multiplier using equivalent bit conversion algorithm.
IEEE J. Solid State Circuits, 2001

An 8-b 100-MSample/s CMOS pipelined folding ADC.
IEEE J. Solid State Circuits, 2001

A 14-b 20-Msamples/s CMOS pipelined ADC.
IEEE J. Solid State Circuits, 2001

2000
A 1-V 6-b 50-MSamples/s current-interpolating CMOS ADC.
IEEE J. Solid State Circuits, 2000

A 1.1-GHz CMOS fractional-N frequency synthesizer with a 3-b third-order ΔΣ modulator.
IEEE J. Solid State Circuits, 2000

A 13-b 40-MSamples/s CMOS pipelined folding ADC with background offset trimming.
IEEE J. Solid State Circuits, 2000

A self-trimming 14-b 100-MS/s CMOS DAC.
IEEE J. Solid State Circuits, 2000

1999
Nyquist-Rate ADC and DAC.
Proceedings of the VLSI Handbook., 1999

A 5-MHz IF digital FM demodulator.
IEEE J. Solid State Circuits, 1999

A 14-b, 100-MS/s CMOS DAC designed for spectral performance.
IEEE J. Solid State Circuits, 1999

1998
A 200-MHz complex number multiplier using redundant binary arithmetic.
IEEE J. Solid State Circuits, 1998

A CMOS 4× speed DVD read channel IC.
IEEE J. Solid State Circuits, 1998

1997
NRZ timing recovery technique for band-limited channels.
IEEE J. Solid State Circuits, 1997

A 15-b, 5-Msample/s low-spurious CMOS ADC.
IEEE J. Solid State Circuits, 1997

1993
Low-distortion Continuous-time R-MOSFET-C Filters.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

Simplified Digital Calibration for Multi-stage Analog-to-digital Converters.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993


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