Hsunwei Hsiung

According to our database1, Hsunwei Hsiung authored at least 5 papers between 2012 and 2015.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2015
A multi-layered methodology for defect-tolerance of datapath modules in processors.
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

2013
Interplay of Failure Rate, Performance, and Test Cost in TCAM under Process Variations.
Proceedings of the 22nd Asian Test Symposium, 2013

A New March Test for Process-Variation Induced Delay Faults in SRAMs.
Proceedings of the 22nd Asian Test Symposium, 2013

2012
Towards systematic roadmaps for networked systems.
Proceedings of the 11th ACM Workshop on Hot Topics in Networks, 2012

Salvaging chips with caches beyond repair.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012


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