Da Cheng

According to our database1, Da Cheng authored at least 23 papers between 2011 and 2022.

Collaborative distances:



In proceedings 
PhD thesis 


On csauthors.net:


F2-Bubbles: Faithful Bubble Set Construction and Flexible Editing.
IEEE Trans. Vis. Comput. Graph., 2022

Residual Current Detection Prototype and Simulation Method in Low Voltage DC System.
IEEE Access, 2022

Toward Using Multi-Modal Machine Learning for User Behavior Prediction in Simulated Smart Home for Extended Reality.
Proceedings of the 2022 IEEE Conference on Virtual Reality and 3D User Interfaces Abstracts and Workshops, 2022

Using Multi-modal Machine Learning for User Behavior Prediction in Simulated Smart Home for Extended Reality.
Proceedings of the Virtual, Augmented and Mixed Reality: Design and Development, 2022

A fast low rank Vandermonde factorization reconstruction method for non-uniformly sampled 2D NMR spectroscopy.
Digit. Signal Process., 2021

A fast Hankel matrix nonconvex factorization reconstruction method with inertia momentum for non-uniformly sampled NMR spectroscopy.
Digit. Signal Process., 2021

Forecasting SQL Query Cost at Twitter.
Proceedings of the IEEE International Conference on Cloud Engineering, 2021

Caladrius: A Performance Modelling Service for Distributed Stream Processing Systems.
Proceedings of the 35th IEEE International Conference on Data Engineering, 2019

Field profiling & monitoring of payload transistors in FPGAs.
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017

EpCom: A parallel community detection approach for epidemic diffusion over social networks.
Proceedings of the 2017 IEEE International Conference on Bioinformatics and Biomedicine, 2017

Architecture for Reliable Scan-Dump in the Presence of Multiple Asynchronous Clock Domains in FPGA SoCs.
Proceedings of the 26th IEEE Asian Test Symposium, 2017

Application debug in FPGAs in the presence of multiple asynchronous clocks.
Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

PPB: Partially-working processors binning for maximizing wafer utilization.
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

Approximate Algorithm for Fast Calculating Voltage Unbalance Factor of Three-Phase Power System.
IEEE Trans. Ind. Informatics, 2014

Maximizing Yield per Area of Highly Parallel CMPs Using Hardware Redundancy.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Optimizing redundancy design for chip-multiprocessors for flexible utility functions.
Proceedings of the 2014 International Test Conference, 2014

Optimal Redundancy Designs for CNFET-Based Circuits.
Proceedings of the 23rd IEEE Asian Test Symposium, 2014

Trading off area, yield and performance via hybrid redundancy in multi-core architectures.
Proceedings of the 31st IEEE VLSI Test Symposium, 2013

Interplay of Failure Rate, Performance, and Test Cost in TCAM under Process Variations.
Proceedings of the 22nd Asian Test Symposium, 2013

A New March Test for Process-Variation Induced Delay Faults in SRAMs.
Proceedings of the 22nd Asian Test Symposium, 2013

Towards systematic roadmaps for networked systems.
Proceedings of the 11th ACM Workshop on Hot Topics in Networks, 2012

A systematic methodology to improve yield per area of highly-parallel CMPs.
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012

A novel software-based defect-tolerance approach for application-specific embedded systems.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011