Hui Wang

Orcid: 0009-0009-0147-6231

Affiliations:

CASTEST Co., Ltd., Beijing, China

According to our database¹, Hui Wang authored at least 6 papers between 2024 and 2026.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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Bibliography

2026

DomSim: Hardware-Aware Hybrid Fault Simulation With Dominator Tree-Guided Partitioning.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., June, 2026

2025

EPICS: Efficient Parallel Pattern Fault Simulation for Sequential Circuits via Strongly Connected Components.

[BibT_eX]

[DOI]

Proceedings of the 62nd ACM/IEEE Design Automation Conference, 2025

MOSS: Multi-Modal Representation Learning on Sequential Circuits.

[BibT_eX]

[DOI]

Proceedings of the 62nd ACM/IEEE Design Automation Conference, 2025

ETPG: Efficient Transition Fault Simulation via Dual-Strategy Pattern Parallelism and Gate Restructuring.

[BibT_eX]

[DOI]

Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025

2024

Efficient Functional Safety Method for Gate-Level Fine-Grained Digital Circuits with ISO-26262.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference in Asia, 2024

DDP-Fsim: Efficient and Scalable Fault Simulation for Deterministic Patterns with Two-Dimensional Parallelism.

[BibT_eX]

[DOI]

Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design, 2024

Hui Wang

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