Zhiteng Chao

Orcid: 0009-0006-2926-7499

According to our database1, Zhiteng Chao authored at least 24 papers between 2020 and 2026.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2026
Arcane: An Assertion Reduction Framework through Semantic Clustering and MCTS-Guided Rule Exploring.
CoRR, May, 2026

From Indiscriminate to Targeted: Efficient RTL Verification via Functionally Key Signal-Driven LLM Assertion Generation.
CoRR, April, 2026

RTLSeek: Boosting the LLM-Based RTL Generation with Multi-Stage Diversity-Oriented Reinforcement Learning.
CoRR, March, 2026

Pecker: Bug Localization Framework for Sequential Designs via Causal Chain Reconstruction.
CoRR, March, 2026

Iterative LLM-Based Assertion Generation Using Syntax-Semantic Representations for Functional Coverage-Guided Verification.
CoRR, February, 2026

CoverAssert: Iterative LLM Assertion Generation Driven by Functional Coverage via Syntax-Semantic Representations.
Proceedings of the Design, Automation & Test in Europe Conference, 2026

Think with Self-Decoupling and Self-Verification: Automated RTL Design with Backtrack-ToT.
Proceedings of the Design, Automation & Test in Europe Conference, 2026

AssertMiner: Module-Level Spec Generation and Assertion Mining using Static Analysis Guided LLMs.
Proceedings of the 31st Asia and South Pacific Design Automation Conference, 2026

2025
InF-ATPG: Intelligent FFR-Driven ATPG with Advanced Circuit Representation Guided Reinforcement Learning.
CoRR, December, 2025

ParaGate: Parasitic-Driven Domain Adaptation Transfer Learning for Netlist Performance Prediction.
CoRR, November, 2025

Memory-Efficient and Adaptive Heterogeneous Framework for Gate-Level Fault Simulation.
ACM Trans. Design Autom. Electr. Syst., September, 2025

AssertFix: Empowering Automated Assertion Fix via Large Language Models.
CoRR, September, 2025

DeepAssert: An LLM-Aided Verification Framework with Fine-Grained Assertion Generation for Modules with Extracted Module Specifications.
CoRR, September, 2025

Extend IVerilog to Support Batch RTL Fault Simulation.
CoRR, May, 2025

A fast test compaction method using dedicated Pure MaxSAT solver embedded in DFT flow.
Integr., 2025

HighTPI: A Hierarchical Graph Based Intelligent Method for Test Point Insertion.
Proceedings of the 43rd IEEE VLSI Test Symposium, 2025

TESLA: Testability Enhancement for Shift-Left Automation via Multi-LLM Collaboration.
Proceedings of the IEEE International Test Conference, 2025

MOSS: Multi-Modal Representation Learning on Sequential Circuits.
Proceedings of the 62nd ACM/IEEE Design Automation Conference, 2025

PastATPG: A Hybrid ATPG Framework for Better Test Compaction with Partial Assignment SAT.
Proceedings of the 62nd ACM/IEEE Design Automation Conference, 2025

AssertGen: Enhancement of LLM-aided Assertion Generation through Cross-Layer Signal Bridging.
Proceedings of the 34th IEEE Asian Test Symposium, 2025

2024
A Static Test Compaction Method Based on GCN Assisted Fault Gate Classification.
Proceedings of the IEEE International Test Conference in Asia, 2024

A Fast Test Compaction Method for Commercial DFT Flow Using Dedicated Pure-MaxSAT Solver.
Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024

2023
A Distributed ATPG System Combining Test Compaction Based on Pure MaxSAT.
Proceedings of the 32nd IEEE Asian Test Symposium, 2023

2020
Optimization Space Exploration of Hardware Design for CRYSTALS-KYBER.
Proceedings of the 29th IEEE Asian Test Symposium, 2020


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