Jing Ye

Orcid: 0000-0002-8023-5090

Affiliations:
  • Chinese Academy of Sciences, Institute of Computing Technology, State Key Laboratory of Processors/State Key Laboratory of Computer Architecture, Beijing, China


According to our database1, Jing Ye authored at least 67 papers between 2008 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2023
A New Reconfigurable True Random Number Generator and Physical Unclonable Function Unified Chip With On-Chip Auto-Calibration.
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2023

Scalable and Conflict-Free NTT Hardware Accelerator Design: Methodology, Proof, and Implementation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., May, 2023

DHSA: efficient doubly homomorphic secure aggregation for cross-silo federated learning.
J. Supercomput., 2023

Chosen ciphertext correlation power analysis on Kyber.
Integr., 2023

SPFL: A Self-purified Federated Learning Method Against Poisoning Attacks.
CoRR, 2023

Online Reliability Evaluation Design: Select Reliable CRPs for Arbiter PUF and Its Variants.
Proceedings of the IEEE European Test Symposium, 2023

Energy-efficient NTT Design with One-bank SRAM and 2-D PE Array.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

A Template Attack on Reduction Without Reference Device on Kyber.
Proceedings of the 32nd IEEE Asian Test Symposium, 2023

Configurable and High-Level Pipelined Lattice-Based Post Quantum Cryptography Hardware Accelerator Design.
Proceedings of the 32nd IEEE Asian Test Symposium, 2023

Message from the Chairs.
Proceedings of the 32nd IEEE Asian Test Symposium, 2023

A Distributed ATPG System Combining Test Compaction Based on Pure MaxSAT.
Proceedings of the 32nd IEEE Asian Test Symposium, 2023

2022
Accurate Reliability Boundary Evaluation of Approximate Arithmetic Circuit.
IEEE Trans. Very Large Scale Integr. Syst., 2022

An Efficient Full Hardware Implementation of Extended Merkle Signature Scheme.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Entropy Sources Based on Silicon Chips: True Random Number Generator and Physical Unclonable Function.
Entropy, 2022

SASH: Efficient secure aggregation based on SHPRG for federated learning.
Proceedings of the Uncertainty in Artificial Intelligence, 2022

Exploring the high-throughput and low-delay hardware design of SM4 on FPGA.
Proceedings of the 19th International SoC Design Conference, 2022

A Voltage Template Attack on the Modular Polynomial Subtraction in Kyber.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2021
Practical Attacks on Deep Neural Networks by Memory Trojaning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Efficient Secure Aggregation Based on SHPRG For Federated Learning.
CoRR, 2021

Reliability Evaluation of Approximate Arithmetic Circuits Based on Signal Probability.
Proceedings of the IEEE International Test Conference in Asia, 2021

ChaoPIM: A PIM-based Protection Framework for DNN Accelerators Using Chaotic Encryption.
Proceedings of the 30th IEEE Asian Test Symposium, 2021

2020
INOR - An Intelligent noise reduction method to defend against adversarial audio examples.
Neurocomputing, 2020

MultiPAD: A Multivariant Partition-Based Method for Audio Adversarial Examples Detection.
IEEE Access, 2020

Sequence Triggered Hardware Trojan in Neural Network Accelerator.
Proceedings of the 38th IEEE VLSI Test Symposium, 2020

Prediction Stability: A New Metric for Quantitatively Evaluating DNN Outputs.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

Privacy Threats and Protection in Machine Learning.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

Optimization Space Exploration of Hardware Design for CRYSTALS-KYBER.
Proceedings of the 29th IEEE Asian Test Symposium, 2020

HRAE: Hardware-assisted Randomization against Adversarial Example Attacks.
Proceedings of the 29th IEEE Asian Test Symposium, 2020

Survey: Hardware Trojan Detection for Netlist.
Proceedings of the 29th IEEE Asian Test Symposium, 2020

2019
PUFPass: A password management mechanism based on software/hardware codesign.
Integr., 2019

Scan Chain Based Attacks and Countermeasures: A Survey.
IEEE Access, 2019

Implementation of Parametric Hardware Trojan in FPGA.
Proceedings of the IEEE International Test Conference in Asia, 2019

Instruction Vulnerability Test and Code Optimization Against DVFS Attack.
Proceedings of the IEEE International Test Conference in Asia, 2019

iATPG: Instruction-level Automatic Test Program Generation for Vulnerabilities under DVFS attack.
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

Memory Trojan Attack on Neural Network Accelerators.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018
Deterministic and Probabilistic Diagnostic Challenge Generation for Arbiter Physical Unclonable Function.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

RT3D: Real-Time 3-D Vehicle Detection in LiDAR Point Cloud for Autonomous Driving.
IEEE Robotics Autom. Lett., 2018

Fault tolerance on-chip: a reliable computing paradigm using self-test, self-diagnosis, and self-repair (3S) approach.
Sci. China Inf. Sci., 2018

Modeling attacks on strong physical unclonable functions strengthened by random number and weak PUF.
Proceedings of the 36th IEEE VLSI Test Symposium, 2018

Grey Zone in Pre-Silicon Hardware Trojan Detection.
Proceedings of the IEEE International Test Conference in Asia, 2018

VarNet: Exploring Variations for Unsupervised Video Prediction.
Proceedings of the 2018 IEEE/RSJ International Conference on Intelligent Robots and Systems, 2018

Hardware Trojan in FPGA CNN Accelerator.
Proceedings of the 27th IEEE Asian Test Symposium, 2018

PUF Based Pay-Per-Device Scheme for IP Protection of CNN Model.
Proceedings of the 27th IEEE Asian Test Symposium, 2018

Bias PUF based Secure Scan Chain Design.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2018

2017
Going Cooler With Timing-Constrained TeSHoP: A Temperature Sensing-Based Hotspot-Driven Placement Technique for FPGAs.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Power-Utility-Driven Write Management for MLC PCM.
ACM J. Emerg. Technol. Comput. Syst., 2017

LAPS: Layout-Aware Path Selection for Post-Silicon Timing Characterization.
IEICE Trans. Inf. Syst., 2017

GeoCueDepth: Exploiting geometric structure cues to estimate depth from a single image.
Proceedings of the 2017 IEEE/RSJ International Conference on Intelligent Robots and Systems, 2017

VPUF: Voter based physical unclonable function with high reliability and modeling attack resistance.
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017

Leveraging FVT-margins in design space exploration for FFGA-based CNN accelerators.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

Fault diagnosis of arbiter physical unclonable function.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Polymorphic PUF: Exploiting reconfigurability of CPU+FPGA SoC to resist modeling attack.
Proceedings of the 2017 Asian Hardware Oriented Security and Trust Symposium, 2017

2016
RPUF: Physical Unclonable Function with Randomized Challenge to resist modeling attack.
Proceedings of the 2016 IEEE Asian Hardware-Oriented Security and Trust, 2016

TeSHoP: A Temperature Sensing based Hotspot-Driven Placement technique for FPGAs.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

DCPUF: Placement and Routing Constraint based Dynamically Configured Physical Unclonable Function on FPGA (Abstact Only).
Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

POSTER: Attack on Non-Linear Physical Unclonable Function.
Proceedings of the 2016 ACM SIGSAC Conference on Computer and Communications Security, 2016

Efficient Attack on Non-linear Current Mirror PUF with Genetic Algorithm.
Proceedings of the 25th IEEE Asian Test Symposium, 2016

2015
Diagnosis and Layout Aware (DLA) Scan Chain Stitching.
IEEE Trans. Very Large Scale Integr. Syst., 2015

OPUF: Obfuscation logic based physical unclonable function.
Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015

2014
Diagnose Failures Caused by Multiple Locations at a Time.
IEEE Trans. Very Large Scale Integr. Syst., 2014

2013
Capturing post-silicon variation by layout-aware path-delay testing.
Proceedings of the Design, Automation and Test in Europe, 2013

2011
On diagnosis of multiple faults using compacted responses.
Proceedings of the Design, Automation and Test in Europe, 2011

2010
Diagnosis of multiple arbitrary faults with mask and reinforcement effect.
Proceedings of the Design, Automation and Test in Europe, 2010

Substantial Fault Pair At-a-Time (SFPAT): An Automatic Diagnostic Pattern Generation Method.
Proceedings of the 19th IEEE Asian Test Symposium, 2010

2008
Diagnosis of Mask-Effect Multiple Timing Faults in Scan Chains.
Proceedings of the 2008 IEEE International Test Conference, 2008

Deterministic Diagnostic Pattern Generation (DDPG) for Compound Defects.
Proceedings of the 2008 IEEE International Test Conference, 2008

Observation Point Oriented Deterministic Diagnosis Pattern Generation (DDPG) for Chain Diagnosis.
Proceedings of the 17th IEEE Asian Test Symposium, 2008


  Loading...