Hung Tien Bui

According to our database1, Hung Tien Bui authored at least 15 papers between 2001 and 2013.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2013
Design of low power 4-bit flash ADC based on standard cells.
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013

2012
Pipelined FPGA design of the Goertzel algorithm for exon prediction.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011
Rapid prototyping of the Goertzel algorithm for hardware acceleration of exon prediction.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2010
Peak-to-peak jitter reduction technique for the Free-Running Period Synthesizer (FRPS).
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Sensorless vector control of PMSG for variable speed wind energy applications.
Proceedings of the 23rd Canadian Conference on Electrical and Computer Engineering, 2010

2008
Design of a High-Speed Differential Frequency-to-Voltage Converter and Its Application in a 5-GHz Frequency-Locked Loop.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008

Design of an all-digital variable length ring oscillator (VLRO) for clock synthesis.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

High speed CDR using a novel binary phase detector with probable-lock-detection.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

2007
A Low-Complexity High-Speed Clock Generator for Dynamic Frequency Scaling of FPGA and Standard-Cell Based Designs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006
High speed differential pulse-width control loop based on frequency-to-voltage converters.
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

Dual-Path and Diode-Tracking Active Inductors for MCML Gates.
Proceedings of the Canadian Conference on Electrical and Computer Engineering, 2006

2005
A Generic Method for Embedded Measurement and Compensation of Process and Temperature Variations in SoCs.
Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 2005

2004
10 GHz PLL Using Active Shunt-Peaked MCML Gates and Improved Frequency Acquisition XOR Phase Detector in 0.18 µm CMOS.
Proceedings of the 4th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'04), 2004

Shunt-peaking in MCML gates and its application in the design of a 20 Gb/s half-rate phase detector.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2001
Five new high-performance multiplexer-based 1-bit full adder cells.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001


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