François R. Boyer

According to our database1, François R. Boyer authored at least 27 papers between 1998 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2019
HPQS: A Fast, High-Capacity, Hybrid Priority Queuing System for High-Speed Networking Devices.
IEEE Access, 2019

A High-Speed, Scalable, and Programmable Traffic Manager Architecture for Flow-Based Networking.
IEEE Access, 2019

Module-per-Object: A Human-Driven Methodology for C++-Based High-Level Synthesis Design.
Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019

2018
A Fast, Single-Instruction-Multiple-Data, Scalable Priority Queue.
IEEE Trans. Very Large Scale Integr. Syst., 2018

HPQ: A High Capacity Hybrid Priority Queue Architecture for High-Speed Network Switches.
Proceedings of the 16th IEEE International New Circuits and Systems Conference, 2018

Extern Objects in P4: an ROHC Header Compression Scheme Case Study.
Proceedings of the 4th IEEE Conference on Network Softwarization and Workshops, 2018

Design of a Low Latency 40 Gb/s Flow-Based Traffic Manager Using High-Level Synthesis.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

P4-Compatible High-Level Synthesis of Low Latency 100 Gb/s Streaming Packet Parsers in FPGAs.
Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018

2017
A high-speed traffic manager architecture for flow-based networking.
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017

2016
Extern Objects in P4: an ROHC Compression Case Study.
CoRR, 2016

A fast systolic priority queue architecture for a flow-based Traffic Manager.
Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016

Performance characterization of an SCMA decoder.
Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016

Node configuration for the Aho-Corasick algorithm in Intrusion Detection Systems.
Proceedings of the 2016 Symposium on Architectures for Networking and Communications Systems, 2016

2013
Design of low power 4-bit flash ADC based on standard cells.
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013

2010
Peak-to-peak jitter reduction technique for the Free-Running Period Synthesizer (FRPS).
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009
Robust estimation of LP parameters in white noise with unknown variance.
Proceedings of the 16th IEEE International Conference on Electronics, 2009

2007
A Low-Complexity High-Speed Clock Generator for Dynamic Frequency Scaling of FPGA and Standard-Cell Based Designs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Iterative Noise-Compensated Method to Improve LPC Based Speech Analysis.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

2006
A 0.8V algorithmically defined buffer and ring oscillator low-energy design for nanometer SoCs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005
Performance Improvement of Configurable Processor Architectures Using a Variable Clock Period.
Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 2005

Implementation of a cycle by cycle variable speed processor.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
ESys.Net: a new solution for embedded systems modeling and simulation.
Proceedings of the 2004 ACM SIGPLAN/SIGBED Conference on Languages, 2004

.NET Framework - A Solution for the Next Generation Tools for System-Level Modeling and Simulation.
Proceedings of the 2004 Design, 2004

2003
SPACE: A Hardware/Software SystemC Modeling Platform Including an RTOS.
Proceedings of the Forum on specification and Design Languages, 2003

2001
Optimal design of synchronous circuits using software pipelining techniques.
ACM Trans. Design Autom. Electr. Syst., 2001

2000
An efficient verification method for a class of multi-phase sequential circuits.
Proceedings of the 2000 7th IEEE International Conference on Electronics, 2000

1998
Optimal design of synchronous circuits using software pipelining techniques.
Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998


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