Yvon Savaria
Orcid: 0000-0002-3404-9959
According to our database1,
Yvon Savaria
authored at least 426 papers
between 1984 and 2024.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 2008, "For contributions to the development of long interconnect VLSI signal processing architectures".
Timeline
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Online presence:
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Bibliography
2024
IEEE Trans. Netw. Serv. Manag., February, 2024
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., February, 2024
Calibration of Ring Oscillator-Based Integrated Temperature Sensors for Power Management Systems.
Sensors, January, 2024
IEEE Trans. Signal Process., 2024
IEEE Trans. Signal Process., 2024
Digital Compensation of Timing Skew Mismatches in Time-Interleaved ADCs by Source Separation.
IEEE Trans. Instrum. Meas., 2024
Enhanced Dynamic Regulation in Buck Converters: Integrating Input-Voltage Feedforward With Voltage-Mode Feedback.
IEEE Access, 2024
IEEE Access, 2024
2023
Delay Mismatch Insensitive Dead Time Generator for High-Voltage Switched-Mode Power Amplifiers.
IEEE Trans. Circuits Syst. I Regul. Pap., April, 2023
An Efficient OpenCL-Based Implementation of a SHA-3 Co-Processor on an FPGA-Centric Platform.
IEEE Trans. Circuits Syst. II Express Briefs, March, 2023
ACM Trans. Archit. Code Optim., March, 2023
IEEE Access, 2023
A Hardware Architecture of a Dynamic Ranking Packet Scheduler for Programmable Network Devices.
IEEE Access, 2023
High-Temperature Fully Integrated Wireless Monitoring Systems for Aerospace Applications.
Proceedings of the IEEE International Conference on Wireless for Space and Extreme Environments, 2023
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023
Low-Energy, Scalable, On-demand State-of-charge Estimation System for Li-ion batteries.
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023
An Area-efficient Memory-based Architecture for P4-programmable Streaming Parsers in FPGAs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Enabling Human Activity Recognition in Smart Public Transportation Systems in Presence of Dataset Imbalance.
Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023
Proceedings of the 6th International Conference on Advanced Communication Technologies and Networking, 2023
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023
2022
A High-Sensitivity Wide Input-Power-Range Ultra-Low-Power RF Energy Harvester for IoT Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
IEEE Trans. Biomed. Circuits Syst., 2022
Sensors, 2022
IEEE Internet Things J., 2022
CoRR, 2022
IEEE Access, 2022
A Hybrid Approach Based on Recurrent Neural Network for Macromodeling of Nonlinear Electronic Circuits.
IEEE Access, 2022
A Versatile SoC/SiP Sensor Interface for Industrial Applications: Implementation Challenges.
IEEE Access, 2022
RLBEEP: Reinforcement-Learning-Based Energy Efficient Control and Routing Protocol for Wireless Sensor Networks.
IEEE Access, 2022
Investigation of Different Integrated Temperature Monitoring Sensors for High-Voltage SoC DC-DC Converters.
Proceedings of the 20th IEEE Interregional NEWCAS Conference, 2022
Low Complexity Shallow Neural Network With Improved False Negative Rate for Cyber Intrusion Detection Systems.
Proceedings of the 20th IEEE Interregional NEWCAS Conference, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
A Templated VHDL Architecture for Terabit/s P4-programmable FPGA-based Packet Parsing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Automatic Detection of People Getting Into a Bus in a SMART Public Transportation System.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022
Proceedings of the 44th Annual International Conference of the IEEE Engineering in Medicine & Biology Society, 2022
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022
2021
Multi-Sensor Track-to-Track Association and Spatial Registration Algorithm Under Incomplete Measurements.
IEEE Trans. Signal Process., 2021
Ring-Oscillator-Based High Accuracy Low Complexity Multichannel Time-to-Digital Converter Architecture for Field-Programmable Gate Arrays.
IEEE Trans. Instrum. Meas., 2021
Power Bound Analysis of a Two-Step MASH Incremental ADC Based on Noise-Shaping SAR ADCs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
IET Comput. Digit. Tech., 2021
Efficient Design Space Exploration of OpenCL Kernels for FPGA Targets Using Black Box Optimization.
IEEE Access, 2021
Proceedings of the 19th IEEE International New Circuits and Systems Conference, 2021
Non-parametric Statistical Static Timing Analysis based on Improved Parallel Monte Carlo.
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021
Thermo-mechanical Analysis and Fatigue Life Prediction for Integrated Circuits (ICs).
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021
Acceleration of the Secure Hash Algorithm-256 (SHA-256) on an FPGA-CPU Cluster Using OpenCL.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Design and Analysis of Combined Input-Voltage Feedforward and PI Controllers for the Buck Converter.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Causal Information Prediction for Analog Circuit Design Using Variable Selection Methods Based on Machine Learning.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Proceedings of the 28th IEEE International Conference on Electronics, 2021
Proceedings of the FPGA '21: The 2021 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Virtual Event, USA, February 28, 2021
Human Activity Recognition and People Count for a SMART Public Transportation System.
Proceedings of the 4th IEEE 5G World Forum, 2021
2020
Optimization of Small-Delay Defects Test Quality by Clock Speed Selection and Proper Masking Based on the Weighted Slack Percentage.
IEEE Trans. Very Large Scale Integr. Syst., 2020
Desynchronized Model Predictive Control for Large Populations of Fans in Server Racks of Datacenters.
IEEE Trans. Smart Grid, 2020
Generic Wireless Power Transfer and Data Communication System Based on a Novel Modulation Technique.
IEEE Trans. Circuits Syst., 2020
Fully Integrated Digital GaN-Based LSK Demodulator for High-Temperature Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2020
Sensors, 2020
Fine resolution delay tuning method to improve the linearity of an unbalanced time-to-digital converter on a Xilinx FPGA.
IET Circuits Devices Syst., 2020
CNN2Gate: Toward Designing a General Framework for Implementation of Convolutional Neural Networks on FPGA.
CoRR, 2020
Indoor Localization Using Channel State Information With Regression Artificial Neural Networks.
Proceedings of the 91st IEEE Vehicular Technology Conference, 2020
Towards GaN500-based High Temperature ICs: Characterization and Modeling up to 600°C.
Proceedings of the 18th IEEE International New Circuits and Systems Conference, 2020
Fully Integrated Dual-Channel Gate Driver and Area Efficient PID Compensator for Surge Tolerant Power Sensor Interface.
Proceedings of the 18th IEEE International New Circuits and Systems Conference, 2020
Proceedings of the 18th IEEE International New Circuits and Systems Conference, 2020
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020
A High Efficiency and Fast Response PLL Based Buck Converter: Implementation and Simulation.
Proceedings of the 11th IEEE Latin American Symposium on Circuits & Systems, 2020
Analog Circuits to Accelerate the Relaxation Process in the Equilibrium Propagation Algorithm.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Self-Adjusting Deadtime Generator for High-Efficiency High-Voltage Switched-Mode Power Amplifiers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the 32nd International Conference on Microelectronics, 2020
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020
Proceedings of the 21st IEEE International Conference on High Performance Switching and Routing, 2020
Proceedings of the FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020
Proceedings of the 28th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2020
Proceedings of the 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2020
On the Use of Interval Arithmetic for the Branch and Bound Delta-Lognormal Parameter Extraction of Rapid Human Movements.
Proceedings of the Lognormality Principle and its Applications in e-Security, 2020
2019
IEEE Trans. Very Large Scale Integr. Syst., 2019
SHIP: A Scalable High-Performance IPv6 Lookup Algorithm That Exploits Prefix Characteristics.
IEEE/ACM Trans. Netw., 2019
Sensors, 2019
Dependability modeling and optimization of triple modular redundancy partitioning for SRAM-based FPGAs.
Reliab. Eng. Syst. Saf., 2019
GaN-based LSK demodulators for wireless data receivers in high-temperature applications.
Microelectron. J., 2019
Multi-PVT-Point Analysis and Comparison of Recent Small-Delay Defect Quality Metrics.
J. Electron. Test., 2019
Energy Efficient Generic Demodulator for High Data Transmission Rate Over an Inductive Link for Implantable Devices.
IEEE Access, 2019
HPQS: A Fast, High-Capacity, Hybrid Priority Queuing System for High-Speed Networking Devices.
IEEE Access, 2019
A High-Speed, Scalable, and Programmable Traffic Manager Architecture for Flow-Based Networking.
IEEE Access, 2019
Towards an Accurate Probabilistic Modeling and Statistical Analysis of Temporal Faults via Temporal Dynamic Fault-Trees (TDFTs).
IEEE Access, 2019
Proceedings of the Large-Scale Annotation of Biomedical Data and Expert Label Synthesis and Hardware Aware Learning for Medical Imaging and Computer Assisted Intervention, 2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
A Prediction Model for Implementing DVS in Single-Rail Bundled-Data Handshake-Free Asynchronous Circuits.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
A Versatile SoC/SiP Sensor Interface for Industrial Applications: Design Considerations.
Proceedings of the 31st International Conference on Microelectronics, 2019
AnARM: A 28nm Energy Efficient ARM Processor Based on Octasic Asynchronous Technology.
Proceedings of the 25th IEEE International Symposium on Asynchronous Circuits and Systems, 2019
Proceedings of the IEEE International Conference on Artificial Intelligence Circuits and Systems, 2019
2018
Electronics and Packaging Intended for Emerging Harsh Environment Applications: A Review.
IEEE Trans. Very Large Scale Integr. Syst., 2018
IEEE Trans. Very Large Scale Integr. Syst., 2018
A 1.5-pJ/bit, 9.04-Mbit/s Carrier-Width Demodulator for Data Transmission Over an Inductive Link Supporting Power and Data Transfer.
IEEE Trans. Circuits Syst. II Express Briefs, 2018
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
A pattern-based routing algorithm for a novel electronic system prototyping platform.
Integr., 2018
Diagnosis algorithms for a reconfigurable and defect tolerant JTAG scan chain in large area integrated circuits.
Integr., 2018
Enhanced Bloom filter utilisation scheme for string matching using a splitting approach.
IET Commun., 2018
Formal Dependability Modeling and Optimization of Scrubbed-Partitioned TMR for SRAM-based FPGAs.
CoRR, 2018
GaN Integration Technology, an Ideal Candidate for High-Temperature Applications: A Review.
IEEE Access, 2018
New Insights Into Soft-Faults Induced Cardiac Pacemakers Malfunctions Analyzed at System-Level via Model Checking.
IEEE Access, 2018
IEEE Access, 2018
Exploiting built-in delay lines for applying launch-on-capture at-speed testing on self-timed circuits.
Proceedings of the 36th IEEE VLSI Test Symposium, 2018
HPQ: A High Capacity Hybrid Priority Queue Architecture for High-Speed Network Switches.
Proceedings of the 16th IEEE International New Circuits and Systems Conference, 2018
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018
Proceedings of the 10th IEEE International Symposium on Turbo Codes & Iterative Information Processing, 2018
A High-Efficiency Ultra-Low-Power CMOS Rectifier for RF Energy Harvesting Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Design of a Low Latency 40 Gb/s Flow-Based Traffic Manager Using High-Level Synthesis.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
High-Temperature Empirical Modeling for the I-V Characteristics of GaN150-Based HEMT.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
High-Temperature Modeling of the I-V Characteristics of GaN150 HEMT Using Machine Learning Techniques.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018
A Low-Latency Memory-Efficient IPv6 Lookup Engine Implemented on FPGA Using High-Level Synthesis.
Proceedings of the 18th IEEE/ACM International Symposium on Cluster, 2018
2017
IEEE Trans. Ind. Informatics, 2017
Formal analysis of SEU mitigation for early dependability and performability analysis of FPGA-based space applications.
J. Appl. Log., 2017
Formal Methods Based Synthesis of Single Event Transient Tolerant Combinational Circuits.
J. Electron. Test., 2017
Extensions to decision-tree based packet classification algorithms to address new classification paradigms.
Comput. Networks, 2017
IEEE Access, 2017
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017
Analysis of SEU propagation in sequential circuits at RTL using Satisfiability Modulo Theories.
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017
Improving performance of SCMA MPA decoders using estimation of conditional probabilities.
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
Proceedings of the 20th IEEE International Symposium on Real-Time Distributed Computing, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Comprehensive analysis of sequential circuits vulnerability to transient faults using SMT.
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017
Analysis of SEU Propagation in Combinational Circuits at RTL Based on Satisfiability Modulo Theories.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017
An FPGA Overlay Architecture for Cost Effective Regular Expression Search (Abstract Only).
Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017
Proceedings of the 30th IEEE Canadian Conference on Electrical and Computer Engineering, 2017
2016
Monitoring Thermal Stress in Wafer-Scale Integrated Circuits by the Attentive Vision Method Using an Infrared Camera.
IEEE Trans. Circuits Syst. Video Technol., 2016
An Asynchronous Delta-Modulator Based A/D Converter for an Electronic System Prototyping Platform.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
A novel spatially configurable differential interface for an electronic system prototyping platform.
Integr., 2016
Proceedings of the 34th IEEE VLSI Test Symposium, 2016
Applying formal verification to early assessment of FPGA-based aerospace applications: Methodology and experience.
Proceedings of the Annual IEEE Systems Conference, 2016
Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016
Towards LTE physical layer virtualization on a COTS multicore platform with efficient scheduling.
Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016
Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016
Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016
Towards efficient and concurrent FFTs implementation on Intel Xeon/MIC clusters for LTE and HPC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
A compact spatially configurable differential input stage for a field programmable interconnection network.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Wireless power transfer through metallic barriers enclosing a harsh environment; feasibility and preliminary results.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Towards formal abstraction, modeling, and analysis of Single Event Transients at RTL.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Investigating the efficiency and accuracy of a data type reduction technique for soft error analysis.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016
Performance analysis of a reduced complexity SCMA decoder exploiting a low-complexity maximum-likelihood approximation.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016
Efficient and accurate analysis of single event transients propagation using SMT-based techniques.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016
Comprehensive non-functional analysis of combinational circuits vulnerability to single event transients.
Proceedings of the 2016 Forum on Specification and Design Languages, 2016
Efficient probabilistic fault tree analysis of safety critical systems via probabilistic model checking.
Proceedings of the 2016 Forum on Specification and Design Languages, 2016
Proceedings of the 2016 IEEE Canadian Conference on Electrical and Computer Engineering, 2016
Memory-Efficient String Matching for Intrusion Detection Systems using a High-Precision Pattern Grouping Algorithm.
Proceedings of the 2016 Symposium on Architectures for Networking and Communications Systems, 2016
Efficient identification of Faces in video Streams using low-Power Multi-Core Devices.
Proceedings of the Handbook of Pattern Recognition and Computer Vision, 5th Ed., 2016
2015
An Interface for Open-Drain Bidirectional Communication in Field Programmable Interconnection Networks.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
Characterizing, modeling, and analyzing soft error propagation in asynchronous and synchronous digital circuits.
Microelectron. Reliab., 2015
Parallel independent FFT implementation on intel processors and Xeon phi for LTE and OFDM systems.
Proceedings of the Nordic Circuits and Systems Conference, 2015
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015
DPDK and MKL; Enabling technologies for near deterministic cloud-based signal processing.
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015
Power-efficient hardware architecture for computing Split-Radix FFTs on highly sparsed spectrum.
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015
Analysis and characterization of data energy tradeoffs: For VLSI architectural agility in C-RAN platforms.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Modeling the faulty behaviour of digital designs using a feed forward neural network approach.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Defect diagnosis algorithms for a field programmable interconnect network embedded in a Very Large Area Integrated Circuit.
Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015
Efficient multilevel formal analysis and estimation of design vulnerability to Single Event Transients.
Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015
Harvesting energy from data lines for avionics applications: Power conversion chain architecture.
Proceedings of the 27th International Conference on Microelectronics, 2015
Towards an accurate reliability, availability and maintainability analysis approach for satellite systems based on probabilistic model checking.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Proceedings of the 2015 NASA/ESA Conference on Adaptive Hardware and Systems, 2015
Proceedings of the Computational Intelligence in Digital and Network Designs and Applications, 2015
2014
Efficient Uniform Quantization Likelihood Evaluation for Particle Filters in Embedded Implementations.
J. Signal Process. Syst., 2014
Optimizing the Parallel Tree-Search for Finding Shortest-Span Error-Correcting CDO Codes.
IEEE Trans. Parallel Distributed Syst., 2014
Determinism Enhancement of AFDX Networks via Frame Insertion and Sub-Virtual Link Aggregation.
IEEE Trans. Ind. Informatics, 2014
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
Mach. Vis. Appl., 2014
A Parallel Systematic Resampling Algorithm for High-Speed Particle Filters in Embedded Systems.
Circuits Syst. Signal Process., 2014
On Delay Faults Affecting I/O Blocks of an SRAM-Based FPGA Due to Ionizing Radiations.
CoRR, 2014
Proceedings of the Structural, Syntactic, and Statistical Pattern Recognition, 2014
Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014
Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014
Design and Test of Adaptive Computing Fabrics for Scalable and High-Efficiency Cognitive SoC Applications.
Proceedings of the IEEE 23rd North Atlantic Test Workshop, 2014
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014
Modeling, analyzing, and abstracting single event transient propagation at gate level.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014
Probabilistic model checking based DAL analysis to optimize a combined TMR-blind-scrubbing mitigation technique for FPGA-based aerospace applications.
Proceedings of the Twelfth ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2014
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014
Abstracting Single Event Transient characteristics variations due to input patterns and fan-out.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Neuromuscular Representation and Synthetic Generation of Handwritten Whiteboard Notes.
Proceedings of the 14th International Conference on Frontiers in Handwriting Recognition, 2014
A data-driven energy efficient and flexible compute fabric architecture: For adaptive computing applied to ULSI of FFT.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014
Constraint-based configuration complexity model for autonomic network configuration management.
Proceedings of the Global Information Infrastructure and Networking Symposium, 2014
2013
Efficient Parallel Search Algorithm for Determining Optimal R=1/2 Systematic Convolutional Self-Doubly Orthogonal Codes.
IEEE Trans. Commun., 2013
A Library-Based Early Soft Error Sensitivity Analysis Technique for SRAM-Based FPGA Design.
J. Electron. Test., 2013
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013
A reformulated systematic resampling algorithm for particle filters and its parallel implementation in an application-specific instruction-set processor.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
A spatiotemporal attention operator for monitoring thermo-mechanical stress in wafer-scale integrated circuits using an infrared camera.
Proceedings of the 8th International Symposium on Image and Signal Processing and Analysis, 2013
Proceedings of the first edition workshop on High performance and programmable networking, 2013
Early Analysis of Soft Error Effects for Aerospace Applications Using Probabilistic Model Checking.
Proceedings of the Formal Techniques for Safety-Critical Systems, 2013
Proceedings of the 2013 Conference on Design and Architectures for Signal and Image Processing, 2013
Proceedings of the 26th IEEE Canadian Conference on Electrical and Computer Engineering CCECE 2013, 2013
2012
Postsilicon Tuning of Standby Supply Voltage in SRAMs to Reduce Yield Losses Due to Parametric Data-Retention Failures.
IEEE Trans. Very Large Scale Integr. Syst., 2012
IEEE Trans. Very Large Scale Integr. Syst., 2012
Real-Time Computation of Local Neighborhood Functions in Application-Specific Instruction-Set Processors.
IEEE Trans. Very Large Scale Integr. Syst., 2012
Efficient Search Algorithm for Determining Optimal R=1/2 Systematic Convolutional Self-Doubly Orthogonal Codes.
IEEE Trans. Commun., 2012
A High-Efficiency Low-Voltage CMOS Rectifier for Harvesting Energy in Implantable Devices.
IEEE Trans. Biomed. Circuits Syst., 2012
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012
A new approach for pin detection for an electronic system prototyping reconfigurable platform.
Proceedings of the 23rd IEEE International Symposium on Rapid System Prototyping, 2012
Proceedings of the 10th IEEE International NEWCAS Conference, 2012
Proceedings of the 10th IEEE International NEWCAS Conference, 2012
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012
Propagating analog signals through a fully digital network on an electronic system prototyping platform.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Two-level configuration for FPGA: A new design methodology based on a computing fabric.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012
Optimal scheduling policy for AFDX End-Systems with virtual links of identical bandwidth allocation gap size.
Proceedings of the 25th IEEE Canadian Conference on Electrical and Computer Engineering, 2012
2011
IEEE Trans. Circuits Syst. II Express Briefs, 2011
IEEE Trans. Biomed. Circuits Syst., 2011
All digital skew tolerant synchronous interfacing methods for high-performance point-to-point communications in deep sub-micron SoCs.
Integr., 2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Activity management in battery-powered embedded systems: A case study of ZigBee® WSN.
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011
SEGP-Finder: Tool for identification of Soft Error Glitch-Propagating paths at gate level.
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011
2010
Crosstalk-Glitch Gating: A Solution for Designing Glitch-Tolerant Asynchronous Handshake Interface Mechanisms for GALS Systems.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
Crosstalk Glitch Propagation Modeling for Asynchronous Interfaces in Globally Asynchronous Locally Synchronous Systems.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
A spatially reconfigurable fast differential interface for a wafer scale configurable platform.
Proceedings of the 17th IEEE International Conference on Electronics, 2010
Proceedings of the 17th IEEE International Conference on Electronics, 2010
2009
High Acceleration for Video Processing Applications Using Specialized Instruction Set Based on Parallelism and Data Reuse.
J. Signal Process. Syst., 2009
Performance Characterization for the Implementation of Content Addressable Memories Based on Parallel Hashing Memories.
Trans. High Perform. Embed. Archit. Compil., 2009
IEEE Trans. Circuits Syst. I Regul. Pap., 2009
Microelectron. J., 2009
Microelectron. J., 2009
Integr., 2009
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
An All-digital Skew-adaptive Clock Scheduling Algorithm for Heterogeneous Multiprocessor Systems on Chips (MPSoCs).
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Proceedings of the 16th IEEE International Conference on Electronics, 2009
A low-area power-efficient CMOS active rectifier for wirelessly powered medical devices.
Proceedings of the 16th IEEE International Conference on Electronics, 2009
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009
2008
IEEE Trans. Instrum. Meas., 2008
On the Design of Undersampling Continuous-Time Bandpass Delta-Sigma Modulators for Gigahertz Frequency A/D Conversion.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008
IEEE Trans. Circuits Syst. I Regul. Pap., 2008
Design of a High-Speed Differential Frequency-to-Voltage Converter and Its Application in a 5-GHz Frequency-Locked Loop.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008
Hardware/software system co-verification of an active reconfigurable board with SystemC-VHDL.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008
Loop-oriented metrics for exploring an application-specific architecture design-space.
Proceedings of the 19th IEEE International Conference on Application-Specific Systems, 2008
A very-high output impedance current mirror for very-low voltage biomedical analog circuits.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008
2007
A Novel Application-specific Instruction-set Processor Design Approach for Video Processing Acceleration.
J. VLSI Signal Process., 2007
IEEE Trans. Consumer Electron., 2007
A high-level requirements engineering methodology for electronic system-level design.
Comput. Electr. Eng., 2007
Ann. des Télécommunications, 2007
Integrated Circuit Trimming Technique for Offset Reduction in a Precision CMOS Amplifier.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
A Low-Complexity High-Speed Clock Generator for Dynamic Frequency Scaling of FPGA and Standard-Cell Based Designs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Crosstalk Effects in Event-Driven Self-Timed Circuits Designed With 90nm CMOS Technology.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the 14th IEEE International Conference on Electronics, 2007
Proceedings of the 14th IEEE International Conference on Electronics, 2007
An FPGA Implementation of a Scalable Network-on-Chip Based on the Token Ring Concept.
Proceedings of the 14th IEEE International Conference on Electronics, 2007
Digital Measurement Technique for Capacitance Variation Detection on Integrated Circuit I/Os.
Proceedings of the 14th IEEE International Conference on Electronics, 2007
Proceedings of the 14th IEEE International Conference on Electronics, 2007
New Analog Test Metrics Based on Probabilistic and Deterministic Combination Approaches.
Proceedings of the 14th IEEE International Conference on Electronics, 2007
2006
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
Motion Compensated Frame Rate Conversion Using a Specialized Instruction Set Processor.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2006
Validation by Fault Injection of a Software Error Detection Technique Dealing with Critical Single Event Upsets.
Proceedings of the 7th Latin American Test Workshop, 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
A 0.8V algorithmically defined buffer and ring oscillator low-energy design for nanometer SoCs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Design exploration with an application-specific instruction-set processor for ELA deinterlacing.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
A Threshold-Based Deinterlacing Algorithm Using Motion Compensation and Directional Interpolation.
Proceedings of the 13th IEEE International Conference on Electronics, 2006
High speed differential pulse-width control loop based on frequency-to-voltage converters.
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006
Evaluation of a Software-Based Error Detection Technique by RT-Level Fault Injection.
Proceedings of the Third IEEE International Workshop on Electronic Design, 2006
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Proceedings of the Canadian Conference on Electrical and Computer Engineering, 2006
2005
Scheduling and optimal register placement for synchronous circuits derived using software pipelining techniques.
ACM Trans. Design Autom. Electr. Syst., 2005
A system level implementation strategy and partitioning heuristic for LUT-based applications.
Comput. Electr. Eng., 2005
Proceedings of the 16th IEEE International Workshop on Rapid System Prototyping (RSP 2005), 2005
Performance Improvement of Configurable Processor Architectures Using a Variable Clock Period.
Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 2005
Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 2005
A Generic Method for Embedded Measurement and Compensation of Process and Temperature Variations in SoCs.
Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 2005
Analysis of Wave-Pipelined Domino Logic Circuit and Clocking Styles Subject to Parametric Variations.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005
Characterization of laser-induced photoexcitation effect on a surrounding CMOS ring oscillator.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Design methods for CMOS low-current finely tunable voltage references covering a wide output range.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Fast parameters optimization of an iterative decoder using a configurable hardware accelerator.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Application specific instruction-set processor generation for video processing based on loop optimization.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the 12th IEEE International Conference on Electronics, 2005
Gate oxide protection in HV CMOS/DMOS integrated circuits: Design and experimental results.
Proceedings of the 12th IEEE International Conference on Electronics, 2005
The Role of Model-Level Transactors and UML in Functional Prototyping of Systems-on-Chip: A Software-Radio Application.
Proceedings of the 2005 Design, 2005
2004
J. Circuits Syst. Comput., 2004
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004
Verification Strategy Determination Using Dependence Analysis of Transaction-Level Models.
Proceedings of the 4th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'04), 2004
Proceedings of the 4th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'04), 2004
An Intellectual Property Module for Auto-Calibration of Time-Interleaved Pipelined Analog-to-Digital Converters.
Proceedings of the 4th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'04), 2004
Proceedings of the 4th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'04), 2004
Proceedings of the 4th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'04), 2004
10 GHz PLL Using Active Shunt-Peaked MCML Gates and Improved Frequency Acquisition XOR Phase Detector in 0.18 µm CMOS.
Proceedings of the 4th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'04), 2004
Assertion-based on-line verification and debug environment for complex hardware systems.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Spurs modeling in direct digital period synthesizers related to phase accumulator truncation.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
An on-chip delay measurements module for nanostructures characterization.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
An ADPLL circuit using a DDPS for genlock applications.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Shunt-peaking in MCML gates and its application in the design of a 20 Gb/s half-rate phase detector.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Performance Evaluation and Failure Rate Prediction for the Soft Implemented Error Detection Technique.
Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004
The Effect of p-Coupling on the Electronic Properties of 1, 4-Dithiol Benzene Stacking.
Proceedings of the 2004 International Conference on MEMS, 2004
Proceedings of the 2004 International Conference on MEMS, 2004
2003
Improvement of sensor accuracy in the case of a variable surface reflectance gradient for active laser range finders.
IEEE Trans. Instrum. Meas., 2003
Methods for minimizing dynamic power consumption in synchronous designs with multiple supply voltages.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003
A Pattern Reordering Approach Based on Ambiguity Detection for Online Category Learning.
IEEE Trans. Pattern Anal. Mach. Intell., 2003
Proceedings of the 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'03), 30 June, 2003
Proceedings of the 2003 International Symposium on System-on-Chip, 2003
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
A CMOS three-state frequency detector complementary to an enhanced linear phase detector for PLL, DLL or high frequency clock skew measurement.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
A hardware-software co-design model for real-time 3D image computation using active laser range finders: a case study.
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003
Unification of basic retiming and supply voltage scaling to minimize dynamic power consumption for synchronous digital designs.
Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003
2002
IEEE Trans. Very Large Scale Integr. Syst., 2002
FPGA Implementation of a Sub-pixel Correction Algorithm for Active Laser Range Finders.
Proceedings of the IAPR Conference on Machine Vision Applications (IAPR MVA 2002), 2002
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
Architecture and performance characterization of hardware and software implementations of the Crozier frequency estimation algorithm.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
Low-voltage bandgap reference with temperature compensation based on a threshold voltage technique.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
A flexible floating-point format for optimizing data-paths and operators in FPGA based DSPs.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2002
Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002
2001
ACM Trans. Design Autom. Electr. Syst., 2001
IEEE J. Solid State Circuits, 2001
Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001
Methods for optimizing register placement in synchronous circuits derived using software pipelining techniques.
Proceedings of the 14th International Symposium on Systems Synthesis, 2001
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001
2000
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Analysis of quantization effects in a digital hardware implementation of a fuzzy ART neural network algorithm.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Proceedings of the 2000 7th IEEE International Conference on Electronics, 2000
Proceedings of the 2000 7th IEEE International Conference on Electronics, 2000
Proceedings of the Eighth International Workshop on Hardware/Software Codesign, 2000
1999
IEEE Trans. Very Large Scale Integr. Syst., 1999
Generalization, discrimination, and multiple categorization using adaptive resonance theory.
IEEE Trans. Neural Networks, 1999
Spatial characterization of process variations via MOS transistor time constants in VLSI and WSI.
IEEE J. Solid State Circuits, 1999
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
Development of a high performance TSPC library for implementation of large digital building blocks.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
Proceedings of the 7th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '99), 1999
Proceedings of the 1999 Design, 1999
1998
Signal Process., 1998
Parallel ultra large scale engine SIMD architecture for real-time digital signal processing applications.
Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998
Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998
Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998
A Comparative Analysis of Fuzzy ART Neural Network Implementations: The Advantages of Reconfigurable Computing.
Proceedings of the 6th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '98), 1998
Reducing Fault Sensitivity of Microprocessor-Based Systems by Modifying Workload Structure.
Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 1998
1997
Pipelined H-trees for high-speed clocking of large integrated systems in presence of process variations.
IEEE Trans. Very Large Scale Integr. Syst., 1997
Proceedings of International Conference on Neural Networks (ICNN'97), 1997
Proceedings of the 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 1997
Are defect-tolerant circuits with redundancy really cost-effective? Complete and realistic cost model.
Proceedings of the 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 1997
1996
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996
J. Electron. Test., 1996
Panel Summaries.
IEEE Des. Test Comput., 1996
Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996
Proceedings of the 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1996
1995
Equivalence Proofs of Some Yield Modeling Methods for Defect-Tolerant Integrated Circuits.
IEEE Trans. Computers, 1995
Producing Reliable Initialization and Test of Sequential Circuits with Pseudorandom Vectors.
IEEE Trans. Computers, 1995
Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995
Proceedings of the 1995 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1995
Proceedings of the 4th Asian Test Symposium (ATS '95), 1995
1994
IEEE Trans. Very Large Scale Integr. Syst., 1994
IEEE Trans. Commun., 1994
IEEE Trans. Commun., 1994
A Fast Method to Evaluate the Optimum Number of Spares in Defect-Tolerant Integrated Circuits.
IEEE Trans. Computers, 1994
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994
Estimation of Simultaneous Switching Power and Ground Noise of Static CMOS Combinational Circuits.
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994
Defect and Fault Tolerant Scan Chains.
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1994
1993
Parallel Regeneration of Interconnections in VLSI & ULSI Circuits.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993
A High Speed Parallel Structure for the Basic Wavelet Transform Algorithm.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993
Initiability: A Measure of Sequential Testability.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993
Some Results on Yield and Local Design Rule Relaxation.
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1993
1992
Performance improvements to VLSI parallel systems, using dynamic concatenation of processing resources.
Parallel Comput., 1992
Heuristic Prediction of the Optimum Number of spares in Defect-Tolerant Integrated Circuits.
J. Circuits Syst. Comput., 1992
J. Electron. Test., 1992
1991
IEEE Trans. Commun., 1991
1989
Proceedings of the Proceedings International Test Conference 1989, 1989
Proceedings of the Proceedings International Test Conference 1989, 1989
1988
IEEE J. Sel. Areas Commun., 1988
1986
Soft-error filtering: A solution to the reliability problem of future VLSI digital circuits.
Proc. IEEE, 1986
IEEE J. Sel. Areas Commun., 1986
1984
A Design for Machines with Built-In Tolerance to Soft Errors.
Proceedings of the Proceedings International Test Conference 1984, 1984