Hyeon Gon Kim

According to our database1, Hyeon Gon Kim authored at least 3 papers in 2016.

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2016
18.4 An 1.1V 68.2GB/s 8Gb Wide-IO2 DRAM with non-contact microbump I/O test scheme.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

18.3 A 1.2V 64Gb 8-channel 256GB/s HBM DRAM with peripheral-base-die architecture and small-swing technique on heavy load interface.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016



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