Tae Sik Yun

According to our database¹, Tae Sik Yun authored at least 3 papers between 2016 and 2020.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

Legend:

Book

In proceedings

Article

PhD thesis

Dataset

Other

Links

On csauthors.net:

Bibliography

2020

22.3 A 128Gb 8-High 512GB/s HBM2E DRAM with a Pseudo Quarter Bank Structure, Power Dispersion and an Instruction-Based At-Speed PMBIST.

[BibT_eX]

[DOI]

Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2016

18.3 A 1.2V 64Gb 8-channel 256GB/s HBM DRAM with peripheral-base-die architecture and small-swing technique on heavy load interface.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

High bandwidth memory(HBM) with TSV technique.

[BibT_eX]

[DOI]

Proceedings of the International SoC Design Conference, 2016

Tae Sik Yun

Timeline

Legend:

Links

On csauthors.net:

Bibliography

Loading...