Hyeong-Ju Kang

According to our database, Hyeong-Ju Kang authored at least 20 papers between 2000 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

AoCStream: All-on-Chip CNN Accelerator with Stream-Based Line-Buffer Architecture and Accelerator-Aware Pruning.

Hyeong-Ju Kang, Byung-Do Yang

Sensors, October, 2023

AoCStream: All-on-Chip CNN Accelerator With Stream-Based Line-Buffer Architecture.

Hyeong-Ju Kang

Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2023

2020

Accelerator-Aware Pruning for Convolutional Neural Networks.

Hyeong-Ju Kang

IEEE Trans. Circuits Syst. Video Technol., 2020

Low-Area and Low-Power Latch-Based Thermometer-Code Shift-Register.

Ki-Chan Woo, Hyeong-Ju Kang, Byung-Do Yang

IEEE Trans. Circuits Syst. II Express Briefs, 2020

2019

Area-Efficient Bidirectional Shift-Register Using Bidirectional Pulsed-Latches.

Ki-Chan Woo, Hyeong-Ju Kang, Byung-Do Yang

IEEE Trans. Circuits Syst. II Express Briefs, 2019

Short floating-point representation for convolutional neural network inference.

Hyeong-Ju Kang

IEICE Electron. Express, 2019

Real-Time Object Detection on 640x480 Image With VGG16+SSD.

Hyeong-Ju Kang

Proceedings of the International Conference on Field-Programmable Technology, 2019

2013

Area-efficient convolutional deinterleaver for mobile TV receiver.

Hyeong-Ju Kang, Hee Suk Seo, Jin Kwak

ACM Trans. Embed. Comput. Syst., 2013

2012

Low-Power Time Deinterleaver for ISDB-T Receiver.

Hyeong-Ju Kang, Byung-Do Yang

IEEE Trans. Circuits Syst. II Express Briefs, 2012

2011

A Low Power Content Addressable Memory Using Low Swing Search Lines.

Byung-Do Yang, Yong-Kyu Lee, Si-Woo Sung, Jae-Joong Min, Jae-Mun Oh, Hyeong-Ju Kang

IEEE Trans. Circuits Syst. I Regul. Pap., 2011

Area-Efficient Prefilter Architecture for a CDMA Receiver.

Hyeong-Ju Kang, Seung Jae Lee, Byung-Do Yang

IEEE Trans. Circuits Syst. II Express Briefs, 2011

2005

SAT-based unbounded symbolic model checking.

Hyeong-Ju Kang, In-Cheol Park

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

A scalable SIMD digital signal processor for high-quality multifunctional printer systems.

Hyeong-Ju Kang, Yongwoo Choi, Kimo Kim, In-Cheol Park, Jung-Wook Kim, Eul-Hwan Lee, Goo-Soo Gahang

Proceedings of the Color Imaging X: Processing, Hardcopy, and Applications, San Jose, 2005

2003

A 24-bit floating-point audio DSP controller supporting fast exponentiation.

Sung-Won Lee, Hyeong-Ju Kang, In-Cheol Park

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Pairing and ordering to reduce hardware complexity in cascade form filter design.

Hyeong-Ju Kang, In-Cheol Park

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2002

Digital filter synthesis based on an algorithm to generate all minimal signed digit representations.

In-Cheol Park, Hyeong-Ju Kang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

A high-speed and low-latency Reed-Solomon decoder based on a dual-line structure.

Hyeong-Ju Kang, In-Cheol Park

Proceedings of the IEEE International Conference on Acoustics, 2002

2001

Multiplier-less IIR filter synthesis algorithms to trade-off the delay and the number of adders.

Hyeong-Ju Kang, In-Cheol Park

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Digital Filter Synthesis Based on Minimal Signed Digit Representation.

In-Cheol Park, Hyeong-Ju Kang

Proceedings of the 38th Design Automation Conference, 2001

2000

FIR Filter Synthesis Algorithms for Minimizing the Delay and the Number of Adders.

Hyeong-Ju Kang, Hansoo Kim, In-Cheol Park

Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000