Hansoo Kim

This page is a disambiguation page, it actually contains mutiple papers from persons of the same or a similar name.

Known people with the same name:

Bibliography

2023
Long-Term Spatiotemporal Oceanographic Data from the Northeast Pacific Ocean: 1980-2022 Reconstruction Based on the Korea Oceanographic Data Center (KODC) Dataset.
Data, 2023

2021
Edge-based procedural textures.
Vis. Comput., 2021

2019
Effective Image Processing Procedure for Skin Lesion Recognition in Contactless Skin Diagnosis Devices.
Proceedings of the 16th International Joint Conference on e-Business and Telecommunications, 2019

2017
Edge-based Inverse Procedural Texture Synthesis
PhD thesis, 2017

2015
PAD-MAC: Primary User Activity-Aware Distributed MAC for Multi-Channel Cognitive Radio Networks.
Sensors, 2015

A scalable architecture for reducing power consumption in pipelined deep packet inspection system.
Microelectron. J., 2015

2014
Reduced Power Consumption via Fewer Memory Accesses for Deep Packet Inspection.
J. Inf. Sci. Eng., 2014

Reduction of Power Consumption for Pipelined DPI Systems on FPGA.
J. Inf. Sci. Eng., 2014

2011
Knowledge mapping model for construction project organizations.
J. Knowl. Manag., 2011

Constructing u-City of Seoul by future foresight analysis.
Concurr. Comput. Pract. Exp., 2011

2010
AirScope: A Micro-scale Urban Air Quality Management System.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2010

2009
A Fully Performance Compatible 45 nm 4-Gigabit Three Dimensional Double-Stacked Multi-Level NAND Flash Memory With Shared Bit-Line Structure.
IEEE J. Solid State Circuits, 2009

2008
A 45nm 4Gb 3-Dimensional Double-Stacked Multi-Level NAND Flash Memory with Shared Bitline Structure.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

AirScope: A Micro-Scale Urban Air Quality Management System.
Proceedings of the Fourth International Conference on e-Science, 2008

2001
High-performance and low-power memory-interface architecture for video processing applications.
IEEE Trans. Circuits Syst. Video Technol., 2001

2000
Array address translation for SDRAM-based video processing applications.
Proceedings of the Visual Communications and Image Processing 2000, 2000

FIR Filter Synthesis Algorithms for Minimizing the Delay and the Number of Adders.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

Multi-thread VLIW processor architecture for HDTV decoding.
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000

1999
Node Sampling Technique to Speed Up Probability-Based Power Estimation Methods.
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999


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