Hyeri Roh
Orcid: 0009-0001-2183-451X
According to our database1,
Hyeri Roh
authored at least 6 papers
between 2023 and 2025.
Collaborative distances:
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Bibliography
2025
A 3ns Idle-Exit Latency 0.28-28Gb/s/pin Single-Ended NRZ Die-to-Die Interface with Energy-Efficient Receiver and Background Noise Compensation.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2025
2024
Flash: A Hybrid Private Inference Protocol for Deep CNNs with High Accuracy and Low Latency on CPU.
CoRR, 2024
Constructing Hardware Accelerators for Number-Theoretic Transform Using High-Level Synthesis.
Proceedings of the 21st International SoC Design Conference, 2024
Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design, 2024
2023
A Context-Aware Readout System for Sparse Touch Sensing Array Using Ultra-Low-Power Always-On Event Detection.
IEEE Trans. Circuits Syst. II Express Briefs, September, 2023
Design of Energy-Efficient Cryptographically Secure Pseudo-Random Number Generators Using High-Level Synthesis.
Proceedings of the 20th International SoC Design Conference, 2023