Hankyu Chi

According to our database1, Hankyu Chi authored at least 8 papers between 2010 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2020
A 1.1-V 10-nm Class 6.4-Gb/s/Pin 16-Gb DDR5 SDRAM With a Phase Rotator-ILO DLL, High-Speed SerDes, and DFE/FFE Equalization Scheme for Rx/Tx.
IEEE J. Solid State Circuits, 2020

2019

2017
29.7 A 2.5GHz injection-locked ADPLL with 197fsrms integrated jitter and -65dBc reference spur using time-division dual calibration.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2016
Design of Silicon Photonic Interconnect ICs in 65-nm CMOS Technology.
IEEE Trans. Very Large Scale Integr. Syst., 2016

2015
A 1.74mW/GHz 0.11-2.5GHz fast-locking, jitter-reducing, 180° phase-shift digital DLL with a window phase detector for LPDDR4 memory controllers.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

2014
A 20-Gb/s 1.27pJ/b low-power optical receiver front-end in 65nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013
12.5-Gb/s analog front-end of an optical transceiver in 0.13-μm CMOS.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2010
A clock synchronization system with IEEE 1588-2008 adapters over existing Gigabit Ethernet equipment.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010


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