Hankyu Chi

According to our database, Hankyu Chi authored at least 10 papers between 2010 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

A 28-Gb/s Single-Ended PAM-4 Receiver With T-Coil-Integrated Continuous-Time Linear Equalizer in 40-nm CMOS Technology.

Taeyang Sim, Sun-Ho Yeom, Hyunwoo Im, Youngmin Oh, Hyeongmin Seo, Hyeongjun Ko, Hankyu Chi, Hae-Kang Jung, Jaeduk Han

IEEE Trans. Circuits Syst. II Express Briefs, March, 2024

2021

A PVT Variation-Robust All-Digital Injection-Locked Clock Multiplier With Real-Time Offset Tracking Using Time-Division Dual Calibration.

Min-Seong Choo, Sungwoo Kim, Han-Gon Ko, Sung-Yong Cho, Kwanseo Park, Jinhyung Lee, Soyeong Shin, Hankyu Chi, Deog-Kyoon Jeong

IEEE J. Solid State Circuits, 2021

2020

A 1.1-V 10-nm Class 6.4-Gb/s/Pin 16-Gb DDR5 SDRAM With a Phase Rotator-ILO DLL, High-Speed SerDes, and DFE/FFE Equalization Scheme for Rx/Tx.

Dongkyun Kim, Kibong Koo, Yongmi Kim, Dong-Uk Lee, Jaejin Lee, Ki Hun Kwon, Byeongchan Choi, Hongjung Kim, Sanghyun Ku, Jong-Sam Kim, Seungwook Oh, Minsu Park, Dain Im, Yongsung Lee, Mingyu Park, Jonghyuck Choi, Junhyun Chun, Kyowon Jin, Sungchun Jang, Jun-Yong Song, Hankyu Chi, Geunho Choi, Sunmyung Choi, Changhyun Kim, Minsik Han

IEEE J. Solid State Circuits, 2020

2019

A 1.1V 1ynm 6.4Gb/s/pin 16Gb DDR5 SDRAM with a Phase-Rotator-Based DLL, High-Speed SerDes and RX/TX Equalization Scheme.

Dongkyun Kim, Minsu Park, Sungchun Jang, Jun-Yong Song, Hankyu Chi, Geunho Choi, Sunmyung Choi, Jaeil Kim, Changhyun Kim, Kyung Whan Kim, Kibong Koo, Seonghwi Song, Yongmi Kim, Dong-Uk Lee, Jaejin Lee, Dae Suk Kim, Ki Hun Kwon, Minsik Han, Byeongchan Choi, Hongjung Kim, Sanghyun Ku, Yeonuk Kim, Jong-Sam Kim, Sanghui Kim, Youngsuk Seo, Seungwook Oh, Dain Im, Haksong Kim, Jonghyuck Choi, Jinil Chung, Changhyun Lee, Yongsung Lee, Joo-Hwan Cho, Junhyun Chun, Jonghoon Oh

Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2017

29.7 A 2.5GHz injection-locked ADPLL with 197fsrms integrated jitter and -65dBc reference spur using time-division dual calibration.

Sungwoo Kim, Han-Gon Ko, Sung-Yong Cho, Jinhyung Lee, Soyeong Shin, Min-Seong Choo, Hankyu Chi, Deog-Kyoon Jeong

Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2016

Design of Silicon Photonic Interconnect ICs in 65-nm CMOS Technology.

Woo-Rham Bae, Gyu-Seob Jeong, Yoonsoo Kim, Hankyu Chi, Deog-Kyoon Jeong

IEEE Trans. Very Large Scale Integr. Syst., 2016

2015

A 1.74mW/GHz 0.11-2.5GHz fast-locking, jitter-reducing, 180° phase-shift digital DLL with a window phase detector for LPDDR4 memory controllers.

Joo-Hyung Chae, Gi-Moon Hong, Jihwan Park, Mino Kim, Hyeongjun Ko, Woo-Yeol Shin, Hankyu Chi, Deog-Kyoon Jeong, Suhwan Kim

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

2014

A 20-Gb/s 1.27pJ/b low-power optical receiver front-end in 65nm CMOS.

Gyu-Seob Jeong, Hankyu Chi, Kyungock Kim, Deog-Kyoon Jeong

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013

12.5-Gb/s analog front-end of an optical transceiver in 0.13-μm CMOS.

Dong-Wook Kim, Hankyu Chi, Yu-Sang Chun, Myung-Heon Chin, Gyungock Kim, Deog-Kyoon Jeong

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2010

A clock synchronization system with IEEE 1588-2008 adapters over existing Gigabit Ethernet equipment.

Jiho Han, Hankyu Chi, Deog-Kyoon Jeong

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010