Hyunjoon Kim
This page is a disambiguation page, it actually contains multiple papers from persons of the same or a similar name.
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Bibliography
2026
CoRR, March, 2026
A Low-Power Single-Ended SAR ADC With Energy-Efficient Differential Switching for Ultrafast X-Ray Imagers.
IEEE Open J. Circuits Syst., 2026
2025
CoRR, December, 2025
An Octave Tuning-Range Frequency Generator Integrating a Quad-Core VCO Using Quad-Mode Coupled Dual-Path Inductor With a Wideband ILFD.
IEEE J. Solid State Circuits, May, 2025
Proceedings of the 33rd ACM International Conference on the Foundations of Software Engineering, 2025
Cooperative Retrieval-Augmented Generation for Question Answering: Mutual Information Exchange and Ranking by Contrasting Layers.
Proceedings of the Advances in Neural Information Processing Systems 38: Annual Conference on Neural Information Processing Systems 2025, 2025
2024
CoRR, 2024
Embedded FPGA Developments in 130nm and 28nm CMOS for Machine Learning in Particle Detector Readout.
CoRR, 2024
Proceedings of the 3rd ACM Workshop on the Security Implications of Deepfakes and Cheapfakes, 2024
2023
BP-SCIM: A Reconfigurable 8T SRAM Macro for Bit-Parallel Searching and Computing In-Memory.
IEEE Trans. Circuits Syst. I Regul. Pap., May, 2023
A 1-16b Reconfigurable 80Kb 7T SRAM-Based Digital Near-Memory Computing Macro for Processing Neural Networks.
IEEE Trans. Circuits Syst. I Regul. Pap., April, 2023
Int. J. Prod. Res., February, 2023
IEEE Access, 2023
DenseCIM: Binary Weighted-Capacitor SRAM Computation-In-Memory with Column-by-Column Dynamic Range Calibration SAR ADC.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
2022
A 64 Kb Reconfigurable Full-Precision Digital ReRAM-Based Compute-In-Memory for Artificial Intelligence Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
SRAM-Based In-Memory Computing Macro Featuring Voltage-Mode Accumulator and Row-by-Row ADC for Processing Neural Networks.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
A Scalable CMOS Ising Computer Featuring Sparse and Reconfigurable Spin Interconnects for Solving Combinatorial Optimization Problems.
IEEE J. Solid State Circuits, 2022
CIM-Spin: A Scalable CMOS Annealing Processor With Digital In-Memory Spin Operators and Register Spins for Combinatorial Optimization Problems.
IEEE J. Solid State Circuits, 2022
A Reconfigurable 16Kb AND8T SRAM Macro With Improved Linearity for Multibit Compute-In Memory of Artificial Intelligence Edge Devices.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022
Hybrid dynamic programming with bounding algorithm for the multi-profit orienteering problem.
Eur. J. Oper. Res., 2022
Optimal sequence for single server scheduling incorporating a rate-modifying activity under job-dependent linear deterioration.
Eur. J. Oper. Res., 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
2021
A Logic-Compatible eDRAM Compute-In-Memory With Embedded ADCs for Processing Neural Networks.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
Colonnade: A Reconfigurable SRAM-Based Digital Bit-Serial Compute-In-Memory Macro for Processing Neural Networks.
IEEE J. Solid State Circuits, 2021
A 252 Spins Scalable CMOS Ising Chip Featuring Sparse and Reconfigurable Spin Interconnects for Combinatorial Optimization Problems.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021
2020
31.2 CIM-Spin: A 0.5-to-1.2V Scalable Annealing Processor Using Digital Compute-In-Memory Spin Operators and Register-Based Spins for Combinatorial Optimization Problems.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
A 16×128 Stochastic-Binary Processing Element Array for Accelerating Stochastic Dot-Product Computation Using 1-16 Bit-Stream Length.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
2019
A Bit-Precision Reconfigurable Digital In-Memory Computing Macro for Energy-Efficient Processing of Artificial Neural Networks.
Proceedings of the 2019 International SoC Design Conference, 2019
A Logic Compatible 4T Dual Embedded DRAM Array for In-Memory Computation of Deep Neural Networks.
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019
A 1-16b Precision Reconfigurable Digital In-Memory Computing Macro Featuring Column-MAC Architecture and Bit-Serial Computation.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019
A 16K SRAM-Based Mixed-Signal In-Memory Computing Macro Featuring Voltage-Mode Accumulator and Row-by-Row ADC.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019
2008
Proceedings of the Fourth International Conference on Autonomic and Autonomous Systems, 2008