Lu Lu
Orcid: 0000-0001-6745-622XAffiliations:
- Nanyang Technological University, School of Electrical and Electronic Engineering, Singapore
According to our database1,
Lu Lu
authored at least 20 papers
between 2018 and 2023.
Collaborative distances:
Collaborative distances:
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on orcid.org
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Bibliography
2023
A 47 TOPS/W 10T SRAM-Based Multi-Bit Signed CIM With Self-Adaptive Bias Voltage Generator for Edge Computing Applications.
IEEE Trans. Circuits Syst. II Express Briefs, September, 2023
BP-SCIM: A Reconfigurable 8T SRAM Macro for Bit-Parallel Searching and Computing In-Memory.
IEEE Trans. Circuits Syst. I Regul. Pap., May, 2023
282-to-607 TOPS/W, 7T-SRAM Based CiM with Reconfigurable Column SAR ADC for Neural Network Processing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
A 129.83 TOPS/W Area Efficient Digital SOT/STT MRAM-Based Computing-In-Memory for Advanced Edge AI Chips.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
A 6T SRAM Based Two-Dimensional Configurable Challenge-Response PUF for Portable Devices.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
A Reconfigurable 16Kb AND8T SRAM Macro With Improved Linearity for Multibit Compute-In Memory of Artificial Intelligence Edge Devices.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022
Proceedings of the 19th International SoC Design Conference, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
2021
A Reconfigurable 4T2R ReRAM Computing In-Memory Macro for Efficient Edge Applications.
IEEE Open J. Circuits Syst., 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
A Multi-Functional 4T2R ReRAM Macro Enabling 2-Dimensional Access and Computing In-Memory.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
2020
A 0.506-pJ 16-kb 8T SRAM With Vertical Read Wordlines and Selective Dual Split Power Lines.
IEEE Trans. Very Large Scale Integr. Syst., 2020
Reconfigurable 2T2R ReRAM Architecture for Versatile Data Storage and Computing In-Memory.
IEEE Trans. Very Large Scale Integr. Syst., 2020
Reconfigurable 2T2R ReRAM with Split Word-Lines for TCAM Operation and In-Memory Computing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the 2020 IEEE Asia Pacific Conference on Circuits and Systems, 2020
2019
Improving uniformity and reliability of SRAM PUFs utilizing device aging phenomenon for unique identifier generation.
Microelectron. J., 2019
A Sequence-Dependent Configurable PUF Based on 6T SRAM for Enhanced Challenge Response Space.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
2018
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018