Taegeun Yoo
Orcid: 0000-0001-9876-7725
According to our database1,
Taegeun Yoo
authored at least 24 papers
between 2011 and 2022.
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Bibliography
2022
A 6T SRAM Based Two-Dimensional Configurable Challenge-Response PUF for Portable Devices.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
A 65-nm 8T SRAM Compute-in-Memory Macro With Column ADCs for Processing Neural Networks.
IEEE J. Solid State Circuits, 2022
2021
A Logic-Compatible eDRAM Compute-In-Memory With Embedded ADCs for Processing Neural Networks.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
Colonnade: A Reconfigurable SRAM-Based Digital Bit-Serial Compute-In-Memory Macro for Processing Neural Networks.
IEEE J. Solid State Circuits, 2021
2020
A 0.506-pJ 16-kb 8T SRAM With Vertical Read Wordlines and Selective Dual Split Power Lines.
IEEE Trans. Very Large Scale Integr. Syst., 2020
A 137-μW 1.78-mm<sup>2</sup> 30-Frames/s Real-Time Gesture Recognition SoC for Smart Devices.
IEEE Trans. Very Large Scale Integr. Syst., 2020
A 0.5 V 8-12 Bit 300 KSPS SAR ADC With Adaptive Conversion Time Detection-and-Control for High Immunity to PVT Variations.
IEEE Access, 2020
Design of Current-Mode 8T SRAM Compute-In-Memory Macro for Processing Neural Networks.
Proceedings of the International SoC Design Conference, 2020
Proceedings of the International SoC Design Conference, 2020
A 16×128 Stochastic-Binary Processing Element Array for Accelerating Stochastic Dot-Product Computation Using 1-16 Bit-Stream Length.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
A 16K Current-Based 8T SRAM Compute-In-Memory Macro with Decoupled Read/Write and 1-5bit Column ADC.
Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020
2019
A Bit-Precision Reconfigurable Digital In-Memory Computing Macro for Energy-Efficient Processing of Artificial Neural Networks.
Proceedings of the 2019 International SoC Design Conference, 2019
A Logic Compatible 4T Dual Embedded DRAM Array for In-Memory Computation of Deep Neural Networks.
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019
A 213.7-µW Gesture Sensing System-On-Chip With Self-Adaptive Motion Detection and Noise-Tolerant Outermost-Edge-Based Feature Extraction in 65 nm.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019
A 1-16b Precision Reconfigurable Digital In-Memory Computing Macro Featuring Column-MAC Architecture and Bit-Serial Computation.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019
2018
A 12-bit Multi-Channel R-R DAC Using a Shared Resistor String Scheme for Area-Efficient Display Source Driver.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
An 88% Efficiency 0.1-300-µW Energy Harvesting System With 3-D MPPT Using Switch Width Modulation for IoT Smart Nodes.
IEEE J. Solid State Circuits, 2018
Proceedings of the International SoC Design Conference, 2018
A 137-μW Area-Efficient Real-Time Gesture Recognition System for Smart Wearable Devices.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018
2017
An 88% efficiency MPPT for PV energy harvesting system with novel switch width modulation for output power 100nW to 0.3mW.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017
2014
A 2 GHz 130 mW Direct-Digital Frequency Synthesizer With a Nonlinear DAC in 55 nm CMOS.
IEEE J. Solid State Circuits, 2014
21.3 A 2GHz 130mW direct-digital frequency synthesizer with a nonlinear DAC in 55nm CMOS.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
2011
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011