Ilan Y. Spillinger

According to our database1, Ilan Y. Spillinger authored at least 17 papers between 1986 and 2000.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of two.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2000
Guest Editors' Introduction.
J. Instr. Level Parallelism, 2000

1996
Retiming revisited and reversed.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

1995
Improving initialization through reversed retiming.
Proceedings of the 1995 European Design and Test Conference, 1995

1994
Performance Evaluation of a Decoded Instruction Cache for Variable Instruction Length Computers.
IEEE Trans. Computers, 1994

A backtracing-oriented procedure for the analysis of combinational gate-level designs.
Integr., 1994

1993
Architectural Improvement for a Data-Driven VLSI Processing Array.
J. Parallel Distributed Comput., 1993

Linear test sequences for detecting functionally faulty RAM's.
Integr., 1993

1991
RIDDLE: A Foundation for Test Generation on a High-Level Design Description.
IEEE Trans. Computers, 1991

Functional Fault Simulation as a Guide for Biased-Random Test Pattern Generation.
IEEE Trans. Computers, 1991

1990
Using functional fault simulation and the difference fault model to estimate implementation fault coverage.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990

1989
Whistle: A Workbench for Test Development of Library-Based Designs.
Computer, 1989

Architectural Improvements for Data-Driven VLSI Processing Arrays.
Proceedings of the fourth international conference on Functional programming languages and computer architecture, 1989

1988
G-RIDDLE : A Formal Analysis of Logic Designs Condiucive to the Acceleration of Backtracing.
Proceedings of the Proceedings International Test Conference 1988, 1988

Delay Test Generation 2: Algebra and Algorithms.
Proceedings of the Proceedings International Test Conference 1988, 1988

Delay Test Generation 1: Concepts and Coverage Metrics.
Proceedings of the Proceedings International Test Conference 1988, 1988

1986
Improving the Performance of a Switch-Level Simulator Targeted for a Logic Simulation Machine.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1986

The Difference Fault Model : Using Functional Fault Simulation to Obtain Implementation Fault Coverage.
Proceedings of the Proceedings International Test Conference 1986, 1986


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