Gabriel M. Silberman

According to our database1, Gabriel M. Silberman authored at least 37 papers between 1982 and 2012.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of one.

Timeline

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PhD thesis 
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Bibliography

2012
The 4x6 Tiered Architecture Method: An Approach to the Design of Enterprise Solutions.
Proceedings of the Advanced Information Systems Engineering Workshops, 2012

2008
Agile architecture methodology: long term strategy interleaved with short term tactics.
Proceedings of the Companion to the 23rd Annual ACM SIGPLAN Conference on Object-Oriented Programming, 2008

2003
Introduction.
Information Systems Frontiers, 2003

2002
Introduction.
Information Systems Frontiers, 2002

2001
New Software Engineering Faculty Symposium.
Proceedings of the 23rd International Conference on Software Engineering, 2001

1997
Foreword to the special issues.
International Journal of Parallel Programming, 1997

Overview: The Centre for Advanced Studies.
IBM Systems Journal, 1997

1996
The Third International Conference on Parallel Computing Technologies (PaCT-95), Saint Petersburg, Russia.
SIGPLAN Notices, 1996

1994
A backtracing-oriented procedure for the analysis of combinational gate-level designs.
Integration, 1994

VLIW Compilation Techniques in a Superscalar Environment.
Proceedings of the ACM SIGPLAN'94 Conference on Programming Language Design and Implementation (PLDI), 1994

1993
Architectural Improvement for a Data-Driven VLSI Processing Array.
J. Parallel Distrib. Comput., 1993

An Architectural Framework for Supporting Heterogeneous Instruction-Set Architectures.
IEEE Computer, 1993

1992
An architectural framework for migration from CISC to higher performance platforms.
Proceedings of the 6th international conference on Supercomputing, 1992

1991
Functional Fault Simulation as a Guide for Biased-Random Test Pattern Generation.
IEEE Trans. Computers, 1991

1990
Using functional fault simulation and the difference fault model to estimate implementation fault coverage.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1990

1989
Whistle: A Workbench for Test Development of Library-Based Designs.
IEEE Computer, 1989

Architectural Improvements for Data-Driven VLSI Processing Arrays.
Proceedings of the fourth international conference on Functional programming languages and computer architecture, 1989

1988
SLS-a fast switch-level simulator [for MOS].
IEEE Trans. on CAD of Integrated Circuits and Systems, 1988

Minimum-Diameter Cyclic Arrangements in Mapping Data-Flow Graphs onto VLSI Arrays.
Mathematical Systems Theory, 1988

A Data-Driven VLSI Array for Arbitrary Algorithms.
IEEE Computer, 1988

G-RIDDLE : A Formal Analysis of Logic Designs Condiucive to the Acceleration of Backtracing.
Proceedings of the Proceedings International Test Conference 1988, 1988

RIDDLE: a foundation for test generation on a high level design description.
Proceedings of the Eighteenth International Symposium on Fault-Tolerant Computing, 1988

1987
The Effect of Operation Scheduling on the Performance of a Data Flow Computer.
IEEE Trans. Computers, 1987

Mapping Data Flow Programs on a VLSI Array of Processors.
Proceedings of the 14th Annual International Symposium on Computer Architecture. Pittsburgh, 1987

An Improved Mapping of Data Flow Programs on a VLSI Array of Processors.
Proceedings of the International Conference on Parallel Processing, 1987

1986
Improving the Performance of a Switch-Level Simulator Targeted for a Logic Simulation Machine.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1986

The Difference Fault Model : Using Functional Fault Simulation to Obtain Implementation Fault Coverage.
Proceedings of the Proceedings International Test Conference 1986, 1986

Efficient Fault Simulation of CMOS Circuits with Accurate Models.
Proceedings of the Proceedings International Test Conference 1986, 1986

SLS - a fast switch level simulator for verification and fault coverage analysis.
Proceedings of the 23rd ACM/IEEE Design Automation Conference. Las Vegas, 1986

1985
Accurate Fault Modeling and Efficient Simulation of Differential CVS Circuits.
Proceedings of the Proceedings International Test Conference 1985, 1985

1984
Embedding Tree Stuctures in VLlSI Hexagonal Arrays.
IEEE Trans. Computers, 1984

Using a Hardware Simulation Engine for Custom MOS Structured Designs.
IBM Journal of Research and Development, 1984

1983
Delayed-Staging Hierarchy Optimization.
IEEE Trans. Computers, 1983

Stack Processing Techniques in Delayed-Staging Storage Hierarchies.
Commun. ACM, 1983

A Direct Mapping of Algorithms onto VLSI Processing Arrays Based on the Data Flow Approach.
Proceedings of the International Conference on Parallel Processing, 1983

Simulating pass transistor circuits using logic simulation machines.
Proceedings of the 20th Design Automation Conference, 1983

1982
Determining Fault Ratios in Multilevel Delayed-Staging Storage Hierarchies.
IEEE Trans. Computers, 1982


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