Chris J. Newburn

Orcid: 0000-0002-8572-9583

Affiliations:
  • NVIDIA Corporation, Santa Clara, CA, USA
  • Intel Corporation, Santa Clara, CA, USA
  • Carnegie Mellon University, Department of Electrical and Computer Engineering, Pittsburgh, PA, USA (PhD)


According to our database1, Chris J. Newburn authored at least 29 papers between 1993 and 2023.

Collaborative distances:

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2023
CODAG: Characterizing and Optimizing Decompression Algorithms for GPUs.
CoRR, 2023

GPU-Initiated On-Demand High-Throughput Storage Access in the BaM System Architecture.
Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2023

2022
GPU-Initiated On-Demand High-Throughput Storage Access in the BaM System Architecture.
Dataset, October, 2022

BaM: A Case for Enabling Fine-grain High Throughput GPU-Orchestrated Access to Storage.
CoRR, 2022

2021
NVIDIA's Cloud Native Supercomputing.
Proceedings of the Driving Scientific and Engineering Discoveries Through the Integration of Experiment, Big Data, and Modeling and Simulation, 2021

2020
Workflows are the New Applications: Challenges in Performance, Portability, and Productivity.
Proceedings of the IEEE/ACM International Workshop on Performance, 2020

An Initial Assessment of NVSHMEM for High Performance Computing.
Proceedings of the 2020 IEEE International Parallel and Distributed Processing Symposium Workshops, 2020

2018
Designing High-Performance In-Memory Key-Value Operations with Persistent GPU Kernels and OpenSHMEM.
Proceedings of the OpenSHMEM and Related Technologies. OpenSHMEM in the Era of Extreme Heterogeneity, 2018

2017
Trends in Data Locality Abstractions for HPC Systems.
IEEE Trans. Parallel Distributed Syst., 2017

GPU-Centric Communication on NVIDIA GPU Clusters with InfiniBand: A Case Study with OpenSHMEM.
Proceedings of the 24th IEEE International Conference on High Performance Computing, 2017

2016
Application Suitability Assessment for Many-Core Targets.
Proceedings of the High Performance Computing, 2016

Heterogeneous Streaming.
Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium Workshops, 2016

LASER: Light, Accurate Sharing dEtection and Repair.
Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016

Portable SIMD Performance with OpenMP* 4.x Compiler Directives.
Proceedings of the Euro-Par 2016: Parallel Processing, 2016

2014
Unification of Static and Dynamic Analyses to Enable Vectorization.
Proceedings of the Languages and Compilers for Parallel Computing, 2014

2013
Offload Compiler Runtime for the Intel Xeon PhiTM Coprocessor.
Proceedings of the Supercomputing - 28th International Supercomputing Conference, 2013

Offload Compiler Runtime for the Intel® Xeon Phi Coprocessor.
Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013

2011
Intel's Array Building Blocks: A retargetable, dynamic compiler and embedded language.
Proceedings of the CGO 2011, 2011

2004
Interaction cost and shotgun profiling.
ACM Trans. Archit. Code Optim., 2004

Interaction Cost: For When Event Counts Just Don't Add Up.
IEEE Micro, 2004

2003
Using Interaction Costs for Microarchitectural Bottleneck Analysis.
Proceedings of the 36th Annual International Symposium on Microarchitecture, 2003

2001
Guest Editors' Introduction.
J. Instr. Level Parallelism, 2001

Stack Value File: Custom Microarchitecture for the Stack.
Proceedings of the Seventh International Symposium on High-Performance Computer Architecture (HPCA'01), 2001

2000
Guest Editors' Introduction.
J. Instr. Level Parallelism, 2000

1997
Post-pass partitioning of signal processing programs.
Int. J. Parallel Program., 1997

Compiler Support for Low-Cost Synchronization Among Threads.
Proceedings of the Parallel Computing: Fundamentals, 1997

1996
Automatic partitioning of signal processing programs for symmetric multiprocessors.
Proceedings of the Fifth International Conference on Parallel Architectures and Compilation Techniques, 1996

1994
A PDG-based Tool and its Use in Analyzing Program Control Dependences.
Proceedings of the Parallel Architectures and Compilation Techniques, 1994

1993
Balancing Fine- and Medium-Grained Parallelism in Scheduling Loops for the XIMD Architecture.
Proceedings of the IFIP WG10.3. Working Conference on Architectures and Compilation Techniques for Fine and Medium Grain Parallelism, 1993


  Loading...