Imad Benacer

Orcid: 0000-0001-9608-2474

According to our database1, Imad Benacer authored at least 10 papers between 2015 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2019
HPQS: A Fast, High-Capacity, Hybrid Priority Queuing System for High-Speed Networking Devices.
IEEE Access, 2019

A High-Speed, Scalable, and Programmable Traffic Manager Architecture for Flow-Based Networking.
IEEE Access, 2019

2018
A Fast, Single-Instruction-Multiple-Data, Scalable Priority Queue.
IEEE Trans. Very Large Scale Integr. Syst., 2018

HPQ: A High Capacity Hybrid Priority Queue Architecture for High-Speed Network Switches.
Proceedings of the 16th IEEE International New Circuits and Systems Conference, 2018

Design of a Low Latency 40 Gb/s Flow-Based Traffic Manager Using High-Level Synthesis.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017
A high-speed traffic manager architecture for flow-based networking.
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017

2016
Extracting parameters of OFET before and after threshold voltage using genetic algorithms.
Int. J. Autom. Comput., 2016

A fast systolic priority queue architecture for a flow-based Traffic Manager.
Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016

2015
Hardware design and FPGA implementation for road plane extraction based on V-disparity approach.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A novel stereovision algorithm for obstacles detection based on U-V-disparity approach.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015


  Loading...