Normand Bélanger
According to our database1,
Normand Bélanger
authored at least 25 papers
between 1994 and 2019.
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Bibliography
2019
SHIP: A Scalable High-Performance IPv6 Lookup Algorithm That Exploits Prefix Characteristics.
IEEE/ACM Trans. Netw., 2019
2018
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
A Low-Latency Memory-Efficient IPv6 Lookup Engine Implemented on FPGA Using High-Level Synthesis.
Proceedings of the 18th IEEE/ACM International Symposium on Cluster, 2018
2017
Extensions to decision-tree based packet classification algorithms to address new classification paradigms.
Comput. Networks, 2017
2016
Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016
Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016
2015
DPDK and MKL; Enabling technologies for near deterministic cloud-based signal processing.
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015
Power-efficient hardware architecture for computing Split-Radix FFTs on highly sparsed spectrum.
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015
2014
Optimizing the Parallel Tree-Search for Finding Shortest-Span Error-Correcting CDO Codes.
IEEE Trans. Parallel Distributed Syst., 2014
2013
Efficient Parallel Search Algorithm for Determining Optimal R=1/2 Systematic Convolutional Self-Doubly Orthogonal Codes.
IEEE Trans. Commun., 2013
Proceedings of the first edition workshop on High performance and programmable networking, 2013
2012
IEEE Trans. Very Large Scale Integr. Syst., 2012
2011
All digital skew tolerant synchronous interfacing methods for high-performance point-to-point communications in deep sub-micron SoCs.
Integr., 2011
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011
2010
Crosstalk-Glitch Gating: A Solution for Designing Glitch-Tolerant Asynchronous Handshake Interface Mechanisms for GALS Systems.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
Crosstalk Glitch Propagation Modeling for Asynchronous Interfaces in Globally Asynchronous Locally Synchronous Systems.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
2009
High Acceleration for Video Processing Applications Using Specialized Instruction Set Based on Parallelism and Data Reuse.
J. Signal Process. Syst., 2009
2008
Loop-oriented metrics for exploring an application-specific architecture design-space.
Proceedings of the 19th IEEE International Conference on Application-Specific Systems, 2008
2007
A Novel Application-specific Instruction-set Processor Design Approach for Video Processing Acceleration.
J. VLSI Signal Process., 2007
Proceedings of the 14th IEEE International Conference on Electronics, 2007
2006
Motion Compensated Frame Rate Conversion Using a Specialized Instruction Set Processor.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2006
Design exploration with an application-specific instruction-set processor for ELA deinterlacing.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
2005
Application specific instruction-set processor generation for video processing based on loop optimization.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
1994
IEEE Trans. Commun., 1994