Irina Alam

Orcid: 0000-0002-7927-8405

According to our database1, Irina Alam authored at least 11 papers between 2017 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
Achieving DRAM-Like PCM by Trading Off Capacity for Latency.
IEEE Trans. Computers, April, 2024

2023
DRDebug: Automated Design Rule Debugging.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., February, 2023

2022
COMET: On-die and In-controller Collaborative Memory ECC Technique for Safer and Stronger Correction of DRAM Errors.
Proceedings of the 52nd Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2022

2021
Designing a 2048-Chiplet, 14336-Core Waferscale Processor.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020
SAME-Infer: Software Assisted Memory Resilience for Efficient Inference at the Edge.
Proceedings of the MEMSYS 2020: The International Symposium on Memory Systems, 2020

2019
Context-Aware Resiliency: Unequal Message Protection for Random-Access Memories.
IEEE Trans. Inf. Theory, 2019

Compression with multi-ECC: enhanced error resiliency for magnetic memories.
Proceedings of the International Symposium on Memory Systems, 2019

2018
Lightweight Fault Tolerance in SRAM Based On-Chip Memories.
PhD thesis, 2018

Error Correction and Detection for Computing Memories Using System Side Information.
Proceedings of the IEEE Information Theory Workshop, 2018

Parity++: Lightweight Error Correction for Last Level Caches.
Proceedings of the 48th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops, 2018

2017
Low-Cost Memory Fault Tolerance for IoT Devices.
ACM Trans. Embed. Comput. Syst., 2017


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