Subramanian S. Iyer
According to our database1,
Subramanian S. Iyer
authored at least 47 papers
between 2000 and 2023.
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Bibliography
2023
A 16-nm 784-Core Digital Signal Processor Array, Assembled as a 2 × 2 Dielet With 10-μm Pitch Interdielet I/O for Runtime Multiprogram Reconfiguration.
IEEE J. Solid State Circuits, 2023
An 8T eNVSRAM Macro in 22nm FDSOI Standard Logic with Simultaneous Full-Array Data Restore for Secure IoT Devices.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
2022
ACM J. Emerg. Technol. Comput. Syst., 2022
A 16nm 785GMACs/J 784-Core Digital Signal Processor Array With a Multilayer Switch Box Interconnect, Assembled as a 2×2 Dielet with 10μm-Pitch Inter-Dielet I/O for Runtime Multi-Program Reconfiguration.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
2021
Large-Scale Quantum System Design on Nb-based Superconducting Silicon Interconnect Fabric.
Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
2019
An Analog Neural Network Computing Engine Using CMOS-Compatible Charge-Trap-Transistor (CTT).
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
Silicon interconnect fabric: A versatile heterogeneous integration platform for AI systems.
IBM J. Res. Dev., 2019
Proceedings of the 21st ACM/IEEE International Workshop on System Level Interconnect Prediction, 2019
Proceedings of the 13th IEEE/ACM International Symposium on Networks-on-Chip, 2019
Proceedings of the IEEE International Reliability Physics Symposium, 2019
Proceedings of the IEEE International Reliability Physics Symposium, 2019
Proceedings of the 25th IEEE International Symposium on High Performance Computer Architecture, 2019
2018
80-kb Logic Embedded High-K Charge Trap Transistor-Based Multi-Time-Programmable Memory With No Added Process Complexity.
IEEE J. Solid State Circuits, 2018
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018
A deep learning approach to spine segmentation using a feed-forward chain of pixel-wise convolutional networks.
Proceedings of the 15th IEEE International Symposium on Biomedical Imaging, 2018
Proceedings of the IEEE International Reliability Physics Symposium, 2018
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018
2017
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
ACM J. Emerg. Technol. Comput. Syst., 2017
Proceedings of the 2017 International Symposium on VLSI Design, Automation and Test, 2017
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
Proceedings of the IEEE International Conference on Rebooting Computing, 2017
2016
IEEE J. Solid State Circuits, 2016
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016
80Kb 10ns read cycle logic Embedded High-K charge trap Multi-Time-Programmable Memory scalable to 14nm FIN with no added process complexity.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016
2015
Oxygen vacancy traps in Hi-K/Metal gate technologies and their potential for embedded memory applications.
Proceedings of the IEEE International Reliability Physics Symposium, 2015
Proceedings of the IEEE International Reliability Physics Symposium, 2015
Proceedings of the 2015 International 3D Systems Integration Conference, 2015
2014
2013
Field Tolerant Dynamic Intrinsic Chip ID Using 32 nm High-K/Metal Gate SOI Embedded DRAM.
IEEE J. Solid State Circuits, 2013
A Self-Authenticating Chip Architecture Using an Intrinsic Fingerprint of Embedded DRAM.
IEEE J. Solid State Circuits, 2013
2012
Proceedings of the Symposium on VLSI Circuits, 2012
Performance analysis and modeling of deep trench decoupling capacitor for 32 nm high-performance SOI processors and beyond.
Proceedings of the IEEE International Conference on IC Design & Technology, 2012
2011
45-nm silicon-on-insulator CMOS technology integrating embedded DRAM for high-performance server and ASIC applications.
IBM J. Res. Dev., 2011
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011
2009
IEEE J. Solid State Circuits, 2009
2008
A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier.
IEEE J. Solid State Circuits, 2008
Analysis of Retention Time Distribution of Embedded DRAM - A New Method to Characterize Across-Chip Threshold Voltage Variation.
Proceedings of the 2008 IEEE International Test Conference, 2008
A Commercial Field-Programmable Dense eFUSE Array Memory with 99.999% Sense Yield for 45nm SOI CMOS.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
2007
A 500MHz Random Cycle 1.5ns-Latency, SOI Embedded DRAM Macro Featuring a 3T Micro Sense Amplifier.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007
2005
IEEE J. Solid State Circuits, 2005
2000
1-GHz fully pipelined 3.7-ns address access time 8 k×1024 embedded synchronous DRAM macro.
IEEE J. Solid State Circuits, 2000