Subramanian S. Iyer

According to our database1, Subramanian S. Iyer authored at least 37 papers between 2005 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2020
A Novel Hierarchical Circuit LUT Model for SOI Technology for Rapid Prototyping.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Accuracy and Resiliency of Analog Compute-in-Memory Inference Engines.
CoRR, 2020

2019
An Analog Neural Network Computing Engine Using CMOS-Compatible Charge-Trap-Transistor (CTT).
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Silicon interconnect fabric: A versatile heterogeneous integration platform for AI systems.
IBM J. Res. Dev., 2019

Communication Considerations for Silicon Interconnect Fabric.
Proceedings of the 21st ACM/IEEE International Workshop on System Level Interconnect Prediction, 2019

Global and semi-global communication on Si-IF.
Proceedings of the 13th IEEE/ACM International Symposium on Networks-on-Chip, 2019

Reliability Evaluation of Silicon Interconnect Fabric Technology.
Proceedings of the IEEE International Reliability Physics Symposium, 2019

Architecting Waferscale Processors - A GPU Case Study.
Proceedings of the 25th IEEE International Symposium on High Performance Computer Architecture, 2019

2018
80-kb Logic Embedded High-K Charge Trap Transistor-Based Multi-Time-Programmable Memory With No Added Process Complexity.
IEEE J. Solid State Circuits, 2018

Network on interconnect fabric.
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018

Reliability challenges in advance packaging.
Proceedings of the IEEE International Reliability Physics Symposium, 2018

A Case for Packageless Processors.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018

2017
Assessing Benefits of a Buried Interconnect Layer in Digital Designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Toward Human-Scale Brain Computing Using 3D Wafer Scale Integration.
ACM J. Emerg. Technol. Comput. Syst., 2017

Heterogeneous SoCs.
Proceedings of the 2017 International Symposium on VLSI Design, Automation and Test, 2017

Integrated neural interfaces.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

Advanced Packaging and Heterogeneous Integration to Reboot Computing.
Proceedings of the IEEE International Conference on Rebooting Computing, 2017

2016
A 14 nm 1.1 Mb Embedded DRAM Macro With 1 ns Access.
IEEE J. Solid State Circuits, 2016

Three-Dimensional Dynamic Random Access Memories Using Through-Silicon-Vias.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016

80Kb 10ns read cycle logic Embedded High-K charge trap Multi-Time-Programmable Memory scalable to 14nm FIN with no added process complexity.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

2015
Oxygen vacancy traps in Hi-K/Metal gate technologies and their potential for embedded memory applications.
Proceedings of the IEEE International Reliability Physics Symposium, 2015

Impact of 3D copper TSV integration on 32SOI FEOL and BEOL reliability.
Proceedings of the IEEE International Reliability Physics Symposium, 2015

2014
Silicon stress: technical perspective.
Commun. ACM, 2014

2013
Field Tolerant Dynamic Intrinsic Chip ID Using 32 nm High-K/Metal Gate SOI Embedded DRAM.
IEEE J. Solid State Circuits, 2013

A Self-Authenticating Chip Architecture Using an Intrinsic Fingerprint of Embedded DRAM.
IEEE J. Solid State Circuits, 2013

2012
Dynamic intrinsic chip ID using 32nm high-K/metal gate SOI embedded DRAM.
Proceedings of the Symposium on VLSI Circuits, 2012

Performance analysis and modeling of deep trench decoupling capacitor for 32 nm high-performance SOI processors and beyond.
Proceedings of the IEEE International Conference on IC Design & Technology, 2012

2011
45-nm silicon-on-insulator CMOS technology integrating embedded DRAM for high-performance server and ASIC applications.
IBM J. Res. Dev., 2011

3D integration review.
Sci. China Inf. Sci., 2011

Three Dimensional integration - Considerations for memory applications.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2009
A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS.
IEEE J. Solid State Circuits, 2009

2008
A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier.
IEEE J. Solid State Circuits, 2008

Analysis of Retention Time Distribution of Embedded DRAM - A New Method to Characterize Across-Chip Threshold Voltage Variation.
Proceedings of the 2008 IEEE International Test Conference, 2008

A Commercial Field-Programmable Dense eFUSE Array Memory with 99.999% Sense Yield for 45nm SOI CMOS.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2007
A 500MHz Random Cycle 1.5ns-Latency, SOI Embedded DRAM Macro Featuring a 3T Micro Sense Amplifier.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

Electrically Programmable Fuse (eFUSE): From Memory Redundancy to Autonomic Chips.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2005
Embedded DRAM: Technology platform for the Blue Gene/L chip.
IBM J. Res. Dev., 2005


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